Sharif Digital Repository

With progress in integrated circuits technology, on chip systems have become operational, and after that, onchip network are as solutions to improve onchip connections and also its scalability. With improving technology, the number of cores on chips can be more, that it causes increasing importance of produced problems by parallel links. Serial links are one of the methods to decrease these problems. Serial links have some advantages in compare with parallel links in some aspects like: clock pulse skew, cross talk, area cost, difficulties in wiring and synchronizing clock pulse signals. But any way, problems such as high operational frequency and complicated serializer and deserializer... 

Injectable hydrogels have emerged as promising candidates for bone tissue engineering due to their compatibility with minimally invasive procedures and ability to conform to irregular bone defects. In this study, a novel temperature-sensitive copolymer based on silk fibroin (PF-127-g-SF) was synthesized and its properties were evaluated. For this purpose, the hydroxyl groups of poloxamer were first modified to carboxylic acid groups (PF-127-COOH), and then grafted onto silk fibroin through a carbodiimide coupling reaction, thereby imparting thermosensitivity to the fibroin structure. The resulting copolymer exhibited a higher sol-gel transition temperature (34 °C at 16% w/v) compared to pure... 

In recent years, environmental concerns regarding the removal of pollutants such as organic dyes and heavy metals from water sources have increased significantly. In this regard, hydrogels based on natural polymers have attracted considerable attention for water treatment applications due to their biodegradability, low toxicity, and desirable stability. Hydrogel beads, with their highly porous structure, provide high adsorption capacity and rapid adsorption kinetics. In this study, hydrogel beads based on alginate and polyvinyl alcohol (PVA) polymers were fabricated as mixed and hybrid composites in the presence of zeolitic imidazolate framework (ZIF-8) and diatomite fillers. For this... 

According to prediction of ITRS, power consumption and bandwidth of processors' interconnection, will be the most major bottleneck of the System-on- Chips (SoCs) in the future. Therefore, in MultiProcessor System-on-Chip (MPSoC) architectures, the design constraints will be altered from "Computational Constraints" to "Communicational Constraints". There are three kinds of communications in the surface of the chip: Global, median and local. The main difference between global and local connections is that the length of latter one will be changed with technology. In other words, it is scalable like processor's elements while the length of global connections is practically constant. Even though... 

According to power limitation on a chip and the need to simultaneously access high utilization and low power consumption, Multi-Processor System-on-Chip (MPSoC) architectures have been introduced. The major part of power consumption in a network on chip belongs to interconnects. One of the most important issues is to decrease power consumption while maintaining high utilization. The ability of optical interconnects in decreasing power consumption and increasing utilization has introduced a new architecture called optical network on chip. This architecture uses the benefits of optical signals and elements in order to transfer data. In this thesis, we introduce a new architecture with... 

Recently, a new tool in the study of two-dimensional continuous phase transition was provided by Schramm-Loewner evolution. The main part of SLE is a conformal map which relates growth process of a two-dimensional simple curve to one-dimensional motion on the real axis (so-called Loewner driving function). Time evolution of this map and Loewner driving function is connected via the Loewner differential equation. It turns out that for a certain class of stochastic and conformally invariant curves in two dimensions, the driving function shows Brownian motion in one dimension. Strength point of SLE comes from this fact that all the geometrical properties of such curves is described through a... 

Schramm Loewner evolution (SLE) is a one-parameter family of random simple curves in the complex plane introduced by Schramm in 1999 which is believed to describe the scaling limit of a variety of domain interfaces at criticality. This thesis is concerned with statistical properties of watersheds dividing drainage basins. The fractal dimension of this model is 1.22 which is consistent with the known fractal dimension for several important models such as Invasion percolation and minimum spanning trees (MST). We present numerical evidences that in the scaling limit this model are SLE curves with =1.73, being the only known physical example of an
SLE with <2. This lies outside the... 

Nowadays by increasing the number of processing cores in system-on-chip, using networks-on-chip, as an optimized interconnection foundation for transferring data between processing cores is inevitable .Based on this, the necessity of designing and implementing an optimized structure for testing network-on-chip, considering various overheads such as power consumption, latency, bandwidth and area, becomes an important issue in designing network-on-chip. The purpose of this project is to design an optimized structure for testing routers and connecting links in network, which considers power consumption overhead, latency and area overhead on one hand, and fault coverage on the other hand.... 

As the number of processing cores on a single chip continues to grow, the need for a high band width, low power communication structure, will be the most important requirements of next generation chip multiprocessors. Today, a major part of power consumption in multi core architectures belongs to interconnects. Due to these facts, reducing consuming power, as well as supporting high performance, is concerned in these architectures. The concept of “network-on-chip” emerged to improve the performance of CMPs. But now a day, considering the circumstances of power budges, it’s incapable of presenting new strategies to decrease consuming power and delay. However, optical interconnects have the... 

Nowadays, a large proportion of the power consumption in high-performance multi-processor architectures on chip belongs to connections. Reducing power consumption while maintaining high efficiency in these architectures is one of the main concerns. Networks on Chip (NoC) originally were introduced to improve efficiency, but now, given the importance of power, we must provide some solutions to reduce power consumption, and delay in NOCs. Connections in chip can be divided into three categories: global, intermediate and local, while the length of global connections is almost constant in different scales, local connections are scalable. As a result improving efficiency of a small number of... 

Brown and Henneaux showed that asymptotic symmetries of asymptotically form a conformal group in two dimensions [1]. Also they could derive classical central charge of theory. Fourteen years later, Maldacena, conjectured that this Holographic correspondence could be true for a specific theory a simplified chromodynamics in the boundary of ), this holographic theory attracted physicist communitee's attention. Many physicists tried to make this conjecture more precise. It is worth to say that, no example of holographic correspondence has been completely proven, till now, Because of the difficulty of the calculation. However these days we consider Madacena conjectrure in any arbitrary... 

In this thesis, a hardware is designed and implemented for testing the perfoemance of MIMO communication systems in LTE standard using SCM channel model. This hardware can be used for measuring the BER of 2x2 wireless systems. This hardware is the first channel emulator, with hardware implementation which is using SCM channel model and implementation of a similar one has not been reported.In addition to the implementation of the mentioned channel emulator, a new approach is used for implementing a Gaussian variate generator (GVG) which is implemented on both FPGA and ASIC and shows better characteristics in comparison with the works done in the past. ASIC implementation of this part is done... 

With constant increase in the rate of VLSI circuits manufactured in sites separate from the designers and computer architects, global concern regarding the possibility of integration of malware by the manufacturing foundries has arisen. Particularly, one main issue that affects reliability of the chips is modifications or additions with malicious intention,known as Hardware Trojans, which are easily applicable during design and manufacturing phase of chips. There has been an increasing fraud in chip-set manufacturing. Hardware Trojans may leak confidential information outside the chip, to the attacker, may alter the function of circuit, or completely fail a system. Hence search for new... 

With the widespread use of mobile applications, multimedia and telecommunications, speed of execution has become important. The computation-intensive portions of applications, i.e., loops, devote a significant percentage of their implementation time. Thus, in this thesis, a new method is introduced which greatly increases the execution speed of the loops. Loops are often implemented on coarse-grained reconfiguration architecture (CGRAs) for acceleration, which is a promising architecture with high performance and high power efficiency in comparison to FPGA. In this regard, to reduce the execution time of two-level nested loops, if there are several innermost loops, first, we fuse them, then... 

Today's latest technology integrated circuits are manufactured for a wide range of applications. With the constant increase in the usage rate of integrated circuits, designing a high reliable system is of utmost importance. The avoidance of counterfeit components is a major challenge of hardware security and trust. Counterfeit components cause lower performance and reduced life span. They are of great concern to the manufacturers and consumers of electronic systems, impacting the security and reliability of these systems. If these parts end up in critical applications like medical systems, satellites, aerospace, or power plants, the results could be catastrophic. So far, there are different... 

With constant increase in the rate of VLSI circuits manufactured in sites separate from the designers and computer architects, global concern regarding the possibility of integration of malware by the manufacturing foundries has arisen. Particularly, one main issue that affects relability of the chips is modifications or additions with malicious intension, known as Harware Trojans, which are easily applicable during design and manufacturing phase of chip. This study intends to introduce a model based on the scan chain, a method is provided for intellectual property protection. Currently available IP protection solutions are usually limited to protect single FPGA configurations and require... 

Nowadays integrated circuits are extremely vulnerable to hardware trojans (HT). Hardware trojans can be injected into the ICs in design or fabricate phase, and damage system’s functionality or security. In this thesis, we first describe hardware trojan definition, classification and types of HTs, negative effects, detection ways and analysis of them. Then we propose a new solution in order to solve the negative points of previous methods  

Recent advances in VLSI technology have led to integrate a few billion transistors on a chip. Systems on Chip provide solutions to the design problems of these systems. As technology scales down to deep sub-micron dimensions, the delay and power consumption of global interconnects become the major bottleneck in SoC design. Networks on Chip (NoCs) have been proposed as an efficient, scalable, modular and reliable solution to provide on chip communication in large VLSI design. The market trend to mobile digital systems and battery-powered devices add power as a new dimension to VLSI design space in addition to speed and area. Interconnect wires dissipate a significant fraction of power...