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    A-CACHE: alternating cache allocation to conduct higher endurance in nvm-based caches

    , Article IEEE Transactions on Circuits and Systems II: Express Briefs ; 2018 ; 15497747 (ISSN) Farbeh, H ; Hosseini Monazzah, A. M ; Aliagha, E ; Cheshmikhani, E ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2018
    Abstract
    Recent developments in Non-Volatile Memories (NVMs) have introduced them as an alternative for SRAMs in on-chip caches. Besides the promising features of NVMs, e.g., near-zero leakage power, immunity to radiation-induced particle strike, and higher density, a major drawback of NVM-based caches is their short lifetime due to limited write endurance. This paper first reveals that in L1 caches, the lifetime of data-cache (D-cache) is about 472x shorter than that of instruction-cache (I-cache) due to extreme imbalance write stress between the two. Then, we propose a technique, so-called Alternating Cache Allocation to Conduct Higher Endurance (A-CACHE), to improve the lifetime of... 

    A system-level framework for analytical and empirical reliability exploration of STT-MRAM caches

    , Article IEEE Transactions on Reliability ; Volume 69, Issue 2 , 2020 , Pages 594-610 Cheshmikhani, E ; Farbeh, H ; Asadi, H ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2020
    Abstract
    Spin-transfer torque magnetic RAM (STT-MRAM) is known as the most promising replacement for static random access memory (SRAM) technology in large last-level cache memories (LLC). Despite its high density, nonvolatility, near-zero leakage power, and immunity to radiation as the major advantages, STT-MRAM-based cache memory suffers from high error rates mainly due to retention failure (RF), read disturbance, and write failure. Existing studies are limited to estimate the rate of only one or two of these error types for STT-MRAM cache. However, the overall vulnerability of STT-MRAM caches, whose estimation is a must to design cost-efficient reliable caches, has not been studied previously. In... 

    A system-level framework for analytical and empirical reliability exploration of stt-mram caches

    , Article IEEE Transactions on Reliability ; 2019 ; 00189529 (ISSN) Cheshmikhani, E ; Farbeh, H ; Asadi, H ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2019
    Abstract
    Spin-transfer torque magnetic RAM (STT-MRAM) is known as the most promising replacement for static random access memory (SRAM) technology in large last-level cache memories (LLC). Despite its high density, nonvolatility, near-zero leakage power, and immunity to radiation as the major advantages, STT-MRAM-based cache memory suffers from high error rates mainly due to retention failure (RF), read disturbance, and write failure. Existing studies are limited to estimate the rate of only one or two of these error types for STT-MRAM cache. However, the overall vulnerability of STT-MRAM caches, whose estimation is a must to design cost-efficient reliable caches, has not been studied previously. In... 

    A system-level framework for analytical and empirical reliability exploration of stt-mram caches

    , Article IEEE Transactions on Reliability ; 2019 ; 00189529 (ISSN) Cheshmikhani, E ; Farbeh, H ; Asadi, H ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2019
    Abstract
    Spin-transfer torque magnetic RAM (STT-MRAM) is known as the most promising replacement for static random access memory (SRAM) technology in large last-level cache memories (LLC). Despite its high density, nonvolatility, near-zero leakage power, and immunity to radiation as the major advantages, STT-MRAM-based cache memory suffers from high error rates mainly due to retention failure (RF), read disturbance, and write failure. Existing studies are limited to estimate the rate of only one or two of these error types for STT-MRAM cache. However, the overall vulnerability of STT-MRAM caches, whose estimation is a must to design cost-efficient reliable caches, has not been studied previously. In... 

    3RSeT: Read disturbance rate reduction in STT-mram caches by selective tag comparison

    , Article IEEE Transactions on Computers ; 2021 ; 00189340 (ISSN) Cheshmikhani, E ; Farbeh, H ; Asadi, H ; Sharif University of Technology
    IEEE Computer Society  2021
    Abstract
    Recent development in memory technologies has introduced Spin-Transfer Torque Magnetic RAM (STT-MRAM) as the most promising replacement for SRAMs in on-chip cache memories. Besides its lower leakage power, higher density, immunity to radiation-induced particles, and non-volatility, an unintentional bit flip during read operation, referred to as read disturbance error, is a severe reliability challenge in STT-MRAM caches. One major source of read disturbance error in STT-MRAM caches is simultaneous accesses to all tags for parallel comparison operation in a cache set, which has not been addressed in previous work. This paper first demonstrates that high read accesses to tag arrays extremely... 

    3RSeT: Read disturbance rate reduction in STT-MRAM caches by selective tag comparison

    , Article IEEE Transactions on Computers ; Volume 71, Issue 6 , 2022 , Pages 1305-1319 ; 00189340 (ISSN) Cheshmikhani, E ; Farbeh, H ; Asadi, H ; Sharif University of Technology
    IEEE Computer Society  2022
    Abstract
    Recent development in memory technologies has introduced Spin-Transfer Torque Magnetic RAM (STT-MRAM) as the most promising replacement for SRAMs in on-chip cache memories. Besides its lower leakage power, higher density, immunity to radiation-induced particles, and non-volatility, an unintentional bit flip during read operation, referred to as read disturbance error, is a severe reliability challenge in STT-MRAM caches. One major source of read disturbance error in STT-MRAM caches is simultaneous accesses to all tags for parallel comparison operation in a cache set, which has not been addressed in previous work. This article first demonstrates that high read accesses to tag array extremely... 

    TA-LRW: A replacement policy for error rate reduction in stt-mram caches

    , Article IEEE Transactions on Computers ; Volume 68, Issue 3 , 2019 , Pages 455-470 ; 00189340 (ISSN) Cheshmikhani, E ; Farbeh, H ; Miremadi, S. G ; Asadi, H ; Sharif University of Technology
    IEEE Computer Society  2019
    Abstract
    As technology process node scales down, on-chip SRAM caches lose their efficiency because of their low scalability, high leakage power, and increasing rate of soft errors. Among emerging memory technologies, Spin-Transfer Torque Magnetic RAM (STT-MRAM) is known as the most promising replacement for SRAM-based cache memories. The main advantages of STT-MRAM are its non-volatility, near-zero leakage power, higher density, soft-error immunity, and higher scalability. Despite these advantages, high error rate in STT-MRAM cells due to retention failure, write failure, and read disturbance threatens the reliability of cache memories built upon STT-MRAM technology. The error rate is significantly... 

    TA-LRW: A replacement policy for error rate reduction in stt-mram caches

    , Article IEEE Transactions on Computers ; Volume 68, Issue 3 , 2019 , Pages 455-470 ; 00189340 (ISSN) Cheshmikhani, E ; Farbeh, H ; Miremadi, S. G ; Asadi, H ; Sharif University of Technology
    IEEE Computer Society  2019
    Abstract
    As technology process node scales down, on-chip SRAM caches lose their efficiency because of their low scalability, high leakage power, and increasing rate of soft errors. Among emerging memory technologies, Spin-Transfer Torque Magnetic RAM (STT-MRAM) is known as the most promising replacement for SRAM-based cache memories. The main advantages of STT-MRAM are its non-volatility, near-zero leakage power, higher density, soft-error immunity, and higher scalability. Despite these advantages, high error rate in STT-MRAM cells due to retention failure, write failure, and read disturbance threatens the reliability of cache memories built upon STT-MRAM technology. The error rate is significantly... 

    TA-LRW: A replacement policy for error rate reduction in STT-MRAM caches

    , Article IEEE Transactions on Computers ; 2018 ; 00189340 (ISSN) Cheshmikhani, E ; Farbeh, H ; Miremadi, S. G ; Asadi, H ; Sharif University of Technology
    IEEE Computer Society  2018
    Abstract
    As technology process node scales down, on-chip SRAM caches lose their efficiency because of their low scalability, high leakage power, and increasing rate of soft errors. Among emerging memory technologies, Spin-Transfer Torque Magnetic RAM (STT-MRAM) is known as the most promising replacement for SRAM-based cache memories. The main advantages of STT-MRAM are its non-volatility, near-zero leakage power, higher density, soft-error immunity, and higher scalability. Despite these advantages, high error rate in STT-MRAM cells due to retention failure, write failure, and read disturbance threatens the reliability of cache memories built upon STT-MRAM technology. The error rate is significantly... 

    Reliability Improvement of STT-MRAM Memories in Data Storage Systems

    , Ph.D. Dissertation Sharif University of Technology Cheshmikhani, Elham (Author) ; Asadi, Hossein (Supervisor) ; Farbeh, Hamed (Co-Supervisor)
    Abstract
    Spin-Transfer Torque Magnetic RAM (STT-MRAM) is known as the most promising replacement for SRAM technology in cache memories. Despite its high-density, non-volatility, near-zero leakage power, and immunity to radiation-induced particle strikes as the major advantages, STT-MRAM-based cache memory suffers from high error rates mainly due to retention failure, read disturbance, and write failure. Despite its high-density, non-volatility, near-zero leakage power, and immunity to radiation as the major advantages, STT-MRAM suffers from high error rates. These errors, which are mainly retention failure, read disturbance, and write failure, are the major reliability challenge in STT-MRAM caches.... 

    Investigating the effects of process variations and system workloads on reliability of STT-RAM caches

    , Article Proceedings - 2016 12th European Dependable Computing Conference, EDCC 2016, 5 September 2016 through 9 September 2016 ; 2016 , Pages 120-129 ; 9781509015825 (ISBN) Cheshmikhani, E ; Hosseini Monazzah, A. M ; Farbeh, H ; Miremadi, S. G ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2016
    Abstract
    In recent years, STT-RAMs have been proposed as a promising replacement for SRAMs in on-chip caches. Although STT-RAMs benefit from high-density, non-volatility, and low-power characteristics, high rates of read disturbances and write failures are the major reliability problems in STTRAM caches. These disturbance/failure rates are directly affected not only by workload behaviors, but also by process variations. Several studies characterized the reliability of STTRAM caches just for one cell, but vulnerability of STT-RAM caches cannot be directly derived from these models. This paper extrapolates the reliability characteristics of one STTRAM cell presented in previous studies to the... 

    Robin: incremental oblique interleaved ECC for reliability improvement in STT-MRAM caches

    , Article Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 21 January 2019 through 24 January 2019 ; 2019 , Pages 173-178 ; 9781450360074 (ISBN) Cheshmikhani, E ; Farbeh, H ; Asadi, H ; ACM SIGDA; Cadence Design Systems, Inc.; CEDA; EIC; IEEE CAS; IPSJ ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2019
    Abstract
    Spin-Transfer Torque Magnetic RAM (STT-MRAM) is a promising alternative for SRAMs in on-chip cache memories. Besides all its advantages, high error rate in STT-MRAM is a major limiting factor for on-chip cache memories. In this paper, we first present a comprehensive analysis that reveals that the conventional Error-Correcting Codes (ECCs) lose their efficiency due to data-dependent error patterns, and then propose an efficient ECC configuration, so-called ROBIN, to improve the correction capability. The evaluations show that the inefficiency of conventional ECC increases the cache error rate by an average of 151.7% while ROBIN reduces this value by more than 28.6x. © 2019 Association for... 

    Dose-dependent effects of nanoscale graphene oxide on reproduction capability of mammals

    , Article Carbon ; Volume 95 , December , 2015 , Pages 309-317 ; 00086223 (ISSN) Akhavan, O ; Ghaderi, E ; Hashemi, E ; Akbari, E ; Sharif University of Technology
    Elsevier Ltd  2015
    Abstract
    In vivo dose-dependent effects of nanoscale graphene oxide (NGO) sheets on reproduction capability of Balb/C mice were investigated. Biodistribution study of the NGO sheets (intravenously injected into male mice at dose of ∼2000 μg/mL or 4 mg/kg of body weight) showed a high graphene uptake in testis. Hence, in vivo effects of the NGO sheets on important characteristics of spermatozoa (including their viability, morphology, kinetics, DNA damage and chromosomal aberration) were evaluated. Significant in vivo effects was found at the injected concentrations ≥200 μg/mL after (e.g., ∼45% reduction in sperm viability and motility at 2000 μg/mL). Observation of remarkable DNA fragmentations and... 

    Accelerated differentiation of neural stem cells into neurons on ginseng-reduced graphene oxide sheets

    , Article Carbon ; Volume 66 , January , 2014 , Pages 395-406 Akhavan, O ; Ghaderi, E ; Abouei, E ; Hatamie, S ; Ghasemi, E ; Sharif University of Technology
    2014
    Abstract
    Asian red ginseng was used for green reduction of chemically exfoliated graphene oxide (GO) into reduced graphene oxide (rGO). The reduction level and electrical conductivity of the ginseng-rGO sheets were comparable to those of hydrazine-rGO ones. Reduction by ginseng resulted in repairing the sp 2 graphitic structure of the rGO, while hydrazine-rGO showed more defects and/or smaller aromatic domains. The ginseng-rGO sheets presented a better stability against aggregation than the hydrazine-rGO ones in an aqueous suspension. Whilst the hydrophobic hydrazine-rGO films exhibited no toxicity against human neural stem cells (hNSCs), the hydrophilic GO and ginseng-rGO films (as more... 

    Contested framings and policy controversies: Analysing biosafety policy-making in Iran

    , Article Science and Public Policy ; Volume 40, Issue 5 , 2013 , Pages 616-627 ; 03023427 (ISSN) Kashani, E. S ; Millstone, E ; Sharif University of Technology
    2013
    Abstract
    Vigorous debates have taken place within and between many countries about regulatory policy regimes covering the assessment and approval of genetically modified (GM) crops. In Iran, a very vigorous and hotly contested policy debate concerning legislation covering GM crops occurred between 2004 and 2009, but it was confined within government circles with almost no public discussion. This paper analyses the Iranian policy-making process in the period 2006-9. It explains how and why a stalemate arose in disputes between ministries and departments. The chosen analytical framework draws mainly on the regulation of technological risks and the analysis of public policy-making. It deploys the... 

    On the possible volumes of μ-way latin trades

    , Article Aequationes Mathematicae ; Volume 63, Issue 3 , 2002 , Pages 303-320 ; 00019054 (ISSN) Adams, P ; Billington, E. J ; Bryant, D. E ; Mahmoodian, E. S ; Sharif University of Technology
    Birkhauser Verlag Basel  2002
    Abstract
    A μ-way latin trade of volume s is a set of μ partial latin rectangles (of inconsequential size) containing exactly the same s filled cells, such that if cell (i, j) is filled, it contains a different entry in each of the μ partial latin rectangles, and such that row i in each of the μ partial latin rectangles contains, set-wise, the same symbols and column j, likewise. In this paper we show that all μ-way latin trades with sufficiently large volumes exist, and state some theorems on the non-existence of μ-way latin trades of certain volumes. We also find the set of possible volumes (that is, the volume spectrum) of μ-way latin trades for μ = 4 and 5. (The case μ = 2 was dealt with by Fu,... 

    The three-way intersection problem for latin squares

    , Article Discrete Mathematics ; Volume 243, Issue 1-3 , 2002 , Pages 1-19 ; 0012365X (ISSN) Adams, P ; Billington, E. J ; Bryant, D. E ; Mahmoodian, E. S ; Sharif University of Technology
    2002
    Abstract
    The set of integers k for which there exist three latin squares of order n having precisely k cells identical, with their remaining n2 -k cells different in all three latin squares, denoted by I3[n], is determined here for all orders n. In particular, it is shown that I3[n] = {0,.,n2 -15}U [n2 - 12,n2-9,n2], for n ≫8. ©2002 Eisevier Science B.V. All rights reserved  

    Integration of spatial fuzzy clustering with level set for segmentation of 2-D angiogram

    , Article IECBES 2014, Conference Proceedings - 2014 IEEE Conference on Biomedical Engineering and Sciences: "Miri, Where Engineering in Medicine and Biology and Humanity Meet", 8 December 2014 through 10 December 2014 ; December , 2015 , Pages 309-314 ; 9781479940844 (ISBN) Ghalehnovi, M ; Zahedi, E ; Fatemizadeh, E ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2015
    Abstract
    Coronary angiography is a vital instrument to detect the prevailing of vascular diseases, and accurate vascular segmentation acts a crucial role for proper quantitative analysis of the vascular tree morphological features. Level set methods are popular for segmenting the coronary arteries, but their performance is related to suitable start-up and optimum setting of regulating parameters, essentially done manually. This research presents a novel fuzzy level set procedure with the objective of segmentation of the coronary artery tree in 2-D X-ray angiography as automatically. It is clever to clearly develop from the early segmentation with spatial fuzzy grouping. The adjusting parameters of... 

    Deep relative attributes

    , Article 13th Asian Conference on Computer Vision, ACCV 2016, 20 November 2016 through 24 November 2016 ; Volume 10115 LNCS , 2017 , Pages 118-133 ; 03029743 (ISSN); 9783319541921 (ISBN) Souri, Y ; Noury, E ; Adeli, E ; Sharif University of Technology
    Springer Verlag  2017
    Abstract
    Visual attributes are great means of describing images or scenes, in a way both humans and computers understand. In order to establish a correspondence between images and to be able to compare the strength of each property between images, relative attributes were introduced. However, since their introduction, hand-crafted and engineered features were used to learn increasingly complex models for the problem of relative attributes. This limits the applicability of those methods for more realistic cases. We introduce a deep neural network architecture for the task of relative attribute prediction. A convolutional neural network (ConvNet) is adopted to learn the features by including an... 

    A public code for astrometric microlensing with contour integration

    , Article Monthly Notices of the Royal Astronomical Society ; Volume 505, Issue 1 , 2021 , Pages 126-135 ; 00358711 (ISSN) Bozza, V ; Khalouei, E ; Bachelet, E ; Sharif University of Technology
    Oxford University Press  2021
    Abstract
    We present the first public code for the calculation of the astrometric centroid shift occurring during microlensing events. The computation is based on the contour integration scheme and covers single and binary lensing of finite sources with arbitrary limb darkening profiles. This allows for general detailed investigations of the impact of finite source size in astrometric binary microlensing. The new code is embedded in version 3.0 of vbbinarylensing, which offers a powerful computational tool for extensive studies of microlensing data from current surveys and future space missions. © 2021 The Author(s) Published by Oxford University Press on behalf of Royal Astronomical Society