Sharif Digital Repository

Multicore processors are widely used in today's real-time embedded systems to satisfy the performance and predictability requirements as well as reduce cost. A vast majority of multicore embedded systems are running several tasks with mixed-criticality, in which the non-functional requirements of the tasks are different or even conflicting. A major challenge in mixed-criticality systems is to maximise the efficiency of shared resources while satisfying the criticality requirements. Shared memory is a key component that should be well managed and memory controller plays the main role in this case. Several memory controllers have been introduced in the literature for multicore processors. In... 

This paper presents a new cache scheme based on varying the size of sets in the set-associative cache hierarchically. In this scheme, all sets at a hierarchical level have same size but are fc times more than the size of sets in the next level of hierarchy where k is called division factor. Therefore the size of tag fields associated to each set is variable and it depends on the hierarchy level of the set it is in. This scheme is proposed to achieve higher hit ratios with respect to the two conventional schemes namely set-associative and direct mapping. The proposed scheme has been simulated with several standard trace files SPEC 2000 and statistics are gathered and analyzed for different... 

2,4,6,8,10,12-Hexanitro-2,4,6,8,10,12-hexaazaisowurtzitane (2,4,6,8,10,12-hexanitro-2,4,6,8,10,12-hexaazatetracyclo dodecane (CL-20)-based polymer/plastic bonded explosives are used in propellant formulation. It can be predicted that CL-20-based nano-polymer/plastic bonded explosives are able to have reduced composite sensitivity and superior mechanical strength. In the current study, we have prepared two kinds of CL-20-based nano-polymer/plastic bonded explosives with ethylene-vinyl acetate copolymer and glycidyl azide polymer via the microemulsion method. Several visual techniques such as SEM/AFM/TEM techniques have been utilized for complete characterization of CL-20-based... 

Dependability evaluation of embedded systems due to the integration of hardware and software parts is difficult to analyze. In this paper, we have proposed an experimental method to determine sensitivity to soft errors in an embedded system exploiting Altera SRAM-based FPGAs. The evaluation is performed using both the hardware and software parts of the embedded system in a single framework. To do this, the HDL hardware model of the target system as well as the C-written software codes of the target system, are required. Both permanent and transient faults are injected into the partially- or fully-synthesizable hardware of the target system and this can be performed during the design cycle of... 

Caches, which are comprised much of a CPU chip area and transistor counts, are reasonable targets for transient single and multiple faults induced from energetic particles. This paper presents: (1) a new fault detection scheme for tag arrays of cache memories and (2) an architectural cache to improve performance as well as dependability. In this architecture, cache space is divided into sets of different sizes and different tag lengths. Using the proposed fault detection scheme, i.e., GParity, when single and multiple errors are detected in a word, the word is rewritten by its correct data from memory and its GParity code is recomputed. The error detection scheme and the cache architecture... 

SRAM cache memories suffer from single event upset (SEU) faults induced by energetic particles such as neutron and alpha particles. To protect these caches, designers often use error detection and correction codes, which typically provide single-bit error detection and even correction. However, these codes have low error detection capability or incur significant performance penalties. In this paper, a protected cache scheme based on the variable associativity of sets is presented. In this scheme, cache space is divided into sets of different sizes with variable tag field lengths. The other remained bits of tags are used for protecting the tag using a new protection code. This leads to... 

In this paper, a new cache placement scheme is proposed to achieve higher hit ratios with respect to the two conventional schemes namely set-associative and direct mapping. Similar to set-associative, in this scheme, cache space is divided into sets of different sizes. Hence, the length of tag fields associated to each set is also variable and depends on the partition it is in. The proposed mapping function has been simulated with some standard trace files and statistics are gathered and analyzed for different cache configurations. The results reveal that the proposed scheme exhibits a higher hit ratio compared to the two well-known mapping schemes, namely set-associative and direct mapping,... 

The size and speed of SRAM caches of embedded systems are increasing in response to demands for higher performance. However, the SRAM caches are vulnerable to soft errors originated from energetic nuclear particles or electrical sources. This paper proposes a new protected cache scheme, which provides high performance as well as high fault detection coverage. In this scheme, the cache space is divided into sets of different sizes. Here, the length of tag fields associated to each set is unique and is different from the other sets. The other remained bits of tags are used for protecting the tag using a fault detection scheme e.g., generalized parity. This leads to protect the cache without... 

System fault-tree analysis is a technique for modeling dependability that is in widespread use. For systems such as embedded systems that include both hardware and software, the integration of hardware and software fault trees has proved problematic. In this paper, we present a method for reliability and safety analysis of embedded systems modeled by SystemC language. The evaluation is based on the fault trees generated from both hardware and software parts of the embedded systems described in the unified language. The unified modeling of both hardware and software of embedded systems using SystemC enables designers to be early aware from the safety and reliability of their designs more... 

Information integrity in cache memories is a fundamental requirement for dependable computing. As caches comprise much of a CPU chip area and transistor counts, they are reasonable targets for single and multiple transient faults. This paper presents: 1) a fault detection scheme for tag arrays of cache memories and 2) an architectural cache to improve dependability as well as performance. In this architecture, cache space is divided into sets of different sizes and different tag lengths. The error detection scheme and the cache architecture have been evaluated using a trace driven simulation with soft error injection and SPEC 2000 applications. The results show that error detection... 

In this study, the effect of different parameters on the fluid transport in a fractured micromodel has been investigated. All experiments in this study have been conducted in a glass micromodel. Since the state of wetting is important in the micromodel, the wetting experiments have been conducted to determine the state of wetting in the micromodel. The used micromodel was wet by water and non-wet regarding normal decane. The fracture network, distribution of pore size, matrix construction, and injection rate are the most important parameters affecting the process. Therefore, the influence of these parameters was studied using five different patterns (A to E). The obtained results from... 

Scaling imbibition curves are of great importance in the characterization and simulation of oil production from naturally fractured reservoirs. Different parameters such as matrix porosity and permeability, oil and water viscosities, matrix dimensions, and oil/water interfacial tensions have an effective on the imbibition process. Studies on the scaling imbibition curves along with the consideration of different assumptions have resulted in various scaling equations. In this work, using an artificial neural network (ANN) method, a novel technique is presented for scaling imbibition recovery curves, which can be used for scaling the experimental and field-scale imbibition cases. The... 

Highly conductive polypyrrole/graphene (PYG) nanocomposite was synthesized with chemical oxidation process via emulsion polymerization and used for the preparation of novel porous conductive gelatin/chitosan-based scaffolds. The effect of PYG loading on various properties of scaffolds was investigated. The obtained results indicated that by introducing PYG into the polymeric matrix, the porosity and swelling capacity decreased while electrical conductivity and Young's modulus demonstrated increasing trend. The in vitro biodegradation test revealed that pure gelatin/chitosan matrix lost 80% of its weight after six weeks in the presence of lysozyme whilst the biodegradation rate was... 

This paper presents two effective methods to reduce power consumption of branch target buffer (BTB): 1) the first method is based on storing distance to next branch address in tag array instead of storing whole branch address, 2) the second method is to use a new field in data array of BTB namely Next Branch Distance (NBD) which holds distance of next branch address from current branch address. When a new hit is performed in BTB, based on NBD field, there would be no access through NBD number of instructions, so BTB can be shutdown not to consume power. The new architecture does not impose extra delay and reduction in prediction accuracy. Both methods were implemented and simulated using... 

This paper presents two effective methods to reduce power consumption of branch target buffer (BTB): 1) the first method is based on storing distance to next branch address in tag array instead of storing whole branch address, 2) the second method is to use a new field in data array of BTB namely Next Branch Distance (NBD) which holds distance of next branch address from current branch address. When a new hit is performed in BTB, based on NBD field, there would be no access through NBD number of instructions, so BTB can be shutdown not to consume power. The new architecture does not impose extra delay and reduction in prediction accuracy. Both methods were implemented and simulated using... 

This paper presents transient and permanent fault injection into Verilog models of digital systems during the design phase by a developed simulation-based fault injection tool called INJECT. With this fault injection tool, it is possible to inject crucial fault models in all abstraction levels (such as swith-level) supported by Verilog HDL. Several fault models for injecting into Verilog models are specified and described. Analyzing the results obtained from the fault injections, using INJECT enables system designers to inform from dependable parameters, such as fault latency, propagation and coverage. As a case study, a 32-bit processor, namely DP32, has been evaluated and effects of faults...