Sharif Digital Repository

Over the Recent Decade, the embedded systems have expanded to include a wide variety of products, ranging from digital cameras, to medical systems, to Radar and telecommunication systems, to sensor networks. Engineers strive to create ever smaller and faster products, many of which, such as battery operated systems, have stringent power requirements. Coupled with increasing pressure to decrease costs and time-to-market, the design constraints of embedded systems pose a serious challenge to embedded systems designers. Dynamic reconfigurable hardware can provide a flexible and efficient platform for satisfying the area, performance, cost, and power requirements of many embedded systems.... 

Many embedded processors are used in harsh environments and their behavior should be investigated against the incidence of common faults. Fault Injection is a prevalent method to do this investigation. Simulation-based fault injection is one of the most prominent forms of fault injection. A fault model is required to do simulation-based fault injection. Simulated faults should have the most similarity to the real faults. Temperature variation and in the extreme case thermal shock is one of the probable faults in harsh environment. In this thesis, we want to propose fault models for thermal shock in various abstraction levels, evaluate and compare these fault models and present methods to use... 

Memory organization plays an important role in embedded systems. Among the various component, memories as principle of consumption large amount of energy, are more important in power consumption, real time feature and fault tolerant of system.so that depend on system application, various configuration of memory organization are used…………. Memory organization issues include memory size, memory management methods, hardware management unit, cache, SPM and theirs subject and so on. This thesis discussed important topics related to energy consumption, real time and fault tolerant feature in memory organization and purposed a Configurable Description of Memory Organization for Low-Energy and... 

One the most important issues in most of embedded systems is reliability and fault tolerance.Ensure of correct operation and evaluate reliability and fault tolerance of embedded proces-sors as a critical part of embedded systems, would be necessary. Fault injection is one themostly used methods for evaluating those features. Using FPGA devices is a good alterna-tive for time consuming simulation-based fault injection method because of their speed. But,there are some critical issues in FPGA-based fault injection methods which are controllabil-ity and observability. In addition to need for efficient and applicable observation and controlmechanism to handle fault injection experiments, a... 

Adiabatic logic families are a group of logic circuits which operate based on adiabatic principles to tremendously reduce power consumption. These families have basic difference with common logic families in transistor level structure and there signals are not quadrangular but trapezoidal. Also, in these systems the source lines and clock pulse are the same. Research on Adiabatic families needs theoretical information in reversible computing. So we will start this project with explaining fundamental information in this field. After that some of these logic families are introduced and three important and widely used of them (SCRL-RERL-2LAL) are chosen to simulate. In each of these families... 

Embedded systems usually need to have a Real-time function so that the time constraint has been one of the most essential attributes of these systems. In the design phase of these systems a scheduler must be presented by the designer so that the observance of system deadlines can be guaranteed( Hard Real-time Systems). Safety-critical applications not only must guarantee system deadlines despite the hard timing constraints in the presence of error, but also must operate correctly and tolerate the error. In some of these applications reducing power consumption is one of the most important objectives because of limited supply energy. The purpose of this project is to firstly study the methods... 

Memories are one of the main component in the embedded systems, and owing to their vulnerability to error, this part of system must be fault tolerant. Single error correction (SEC) codes are one of the most commonly used methods against sot errors. However, on the other hands as the technology scales, multiple bit upsets (MBUs) are becoming more likely to occur in the memories and the SEC codes have lost their effectiveness in fault coverage. Therefore a greater attention is devoted to the codes with the higher fault coverage such as single error correction/double error detection (SEC/DED) codes. These codes increase the delay, area and power consumption overhead. These parameters are the... 

Temporary or permanent overload commonly occurs in soft real-time systems. In such situations,the scheduler cannot guarantee the completion of all tasks prior to their deadlines.Hence, some tasks are usually aborted before or during the execution with the aim of maximizing system utility. For this purpose, time-utility function (TUF) of tasks is used to determine how to maximize the accrual utility of the system. Tasks which can provide more utility are more preferable for execution. Previous works on utility accrual maximizing algorithms have not considered memory allocation in accruing utility of soft real time systems. In this thesis, we present an online scheme for multicore embedded... 

Technology scaling allows integrating multiple cores onto a single chip to make the mainstream for advanced embedded systems. However, technology scaling is envisaged to aggravate the reliability of on-chip systems due to increasing transient fault rate due to lower voltages and shrinking transistor dimensions that lead to smaller critical charges. Transient faults are typically resulted due to high-energy particle strikes in hardware and manifest as bit flips. Multi-core systems provide a great opportunity to implement reliability mechanisms such as redundant multithreading (RMT) and process level redundancy. Task replication (e.g. RMT) is a well-established technique to achieve high... 

VLSI technology scaling has resulted in the integration of a larger number of cores in a single chip in successive technology nodes, offering a great potential to realize task-level redundancy for reliability enhancement in safety-critical applications. However, since battery technology no longer advances commensurately with integration density, multi-core platforms may have limited utility in battery-powered embedded systems. In this thesis, we propose an energy-budget-aware reliability management (enBudRM) method for multi-core embedded systems featuring hybrid energy source (with renewable and non-renewable energy sources). Our method is composed of two phases. In the offline phase, we... 

Spin-Transfer-Torque-RAM (STT-RAM) has recently been widely accepted as a promising replacement for SRAM technology through the technology scaling due to its high density, zero standby power and comparable-to-SRAM read access latency. However, there are two major obstacles to use STT-RAM, namely, high write access latency and energy. In this study, we propose two approaches to solve these challenges in embedded systems. The conventional latency of the STT-RAM write operation is 10ns and lowering the write latency causes the required write current exponentially increase, leading to a larger memory cell area and a shorter memory lifetime. As the first proposed method, we have assessed the... 

Many embedded multicore systems can benefit from a memory hierarchy to bridge the processor/memory speed gap. Embedded systems usually utilize a cacheless architecture to avoid the unpredictable behavior. Unlike caches, scratchpad memories (SPM) are software controlled and hence the execution time of applications on such systems can be accurately predicted. Scheduling the tasks of an embedded multicore application and partitioning the available SPM budget among these cores are two critical issues in such systems. Often, these are considered separately, such a decoupled approach may miss better quality schedules. In this paper, we present an integrated approach to task scheduling and SPM... 

Mixed-criticality systems are introduced due to industrial interest to integrate different types of functionalities with varying importance into a common and shared computing platform. Low-energy consumption is vital in mixed-criticality systems due to their ever-increasing computation requirements and the fact that they are mostly supplied with batteries. In this thesis, we propose a novel reliability-aware energy management approach and three methods, Fair-DVFS, Stretch, and Combined Fair-DVFS/Stretch in which energy management targets non-safety-critical functionalities. The Fair-DVFS method lowers energy consumption by evenly distributing slack times between low-criticality tasks while... 

Embedded systems usually have limited energy budget, therefore energy management for these systems is important. On the other hand, many embedded systems have real-time and reliability constraints and such constraints are usually serious obstacles to effective energy management. Considering these tradeoffs between energy consumption and system reliability and timeliness, in this thesis, we consider system-level energy management techniques for embedded systems with both hard real-time and soft real-time tasks. Due to large search space of the problem, we use Genetic Algorithm in our proposed technique. Our proposed energy management technique guarantees the deadlines of hard real-time tasks... 

Embedded systems play an important role in many applications in various areas of human life. A large group of these systems are portable devices that have limited energy budget and therefore require considering the energy consumption in their design. Today, memories are responsible for a considerable portion of energy consumption in embedded systems, mainly because of their static leakage power consumption. Memories used in embedded systems are usually based on either SRAM (mostly used on-chip as cache or scratchpad memory) or DRAM (mostly used off-chip as main memory). The high leakage power of these memories (especially SRAM) is not negligible and hence has persuaded researchers to find... 

Due to the continuing progress in CMOS technology and increased number of cores within a chip, multiple components with different levels of criticality have been integrated into a common hardware platform. These systems with these characteristics are known as Mixed-Criticality Systems (MCS). Also, due to the migration towards multi-core systems, power consumption and specifically instantaneous power consumption is the main concern. To avoid the use of cooling technology, we need to reduce the instantaneous power consumption of the system. However, most existing approaches in MCS have paid attention to reliability guaranteed and energy minimization. Therefore, we consider a dynamic scheduling... 

Mixed-Criticality Systems (MCSs) include tasks that have multiple levels of criticality and they operate in dierent modes. These systems bring benets such as energy and resource cost saving. However, there are challenges in how to manage available resources in order to achieve high utilization, low power consumption, and required reliability. In many cases, these goals are in conict with each other. For example, if ermal Design Power (TDP) was a constraint on the power consumption of the chip, an approach that increases the utilization, unaware of power consumption, can oversteps TDP and leads to permanent or transient faults. Hence aging balancing and task re-execution are utilized to... 

Embedded real-time systems have limitations on power consumption, mainly due to battery usage and temperature constraints. In addition, a large part of these systems has timing constraints. These constraints should be considered when we use power management techniques. Nowadays, due to the use of fault-tolerance techniques, power consumption and especially peak power consumption are increased so it can miss Thermal Design Power constraint. Recently, due to the conservative design of TDP for chips, it is not considered, and hence, a new power constraint as Thermal Safe Power is defined for thermal and power characteristic of the system. The purpose of this study is to define an optimization... 

Number of smart devices is increasing due to the expanding use and vast variety of Internet of Things (IoT) applications. One of the most important challenges in IoT applications is finding the best route for information flow, among a large number of devices with different features.In 2012, the Internet Engineering Task Force (IETF) standardized and introduced the routing protocol for low-power and lossy networks (RPL). Low setup time and loop avoidance are two advantages of RPL. However, in RPL, unbalanced loads on the network causes congestion on some routes, resulting in the loss of many packets. Therefore, due to congestion in the nodes, RPL does not provide much reliability. In... 

In recent years, heterogeneous architectures have been widely used in digital system design, so that these heterogeneous platforms are employed to achieve low power consumption, high performance, and high reliability. In other words, heterogeneous multi-core systems are promising solutions to provide a wide range of possibilities in compromising the low power/energy consumption, high reliability, and high performance. Most heterogeneous systems have several different islands (in terms of core types, supply voltage, and frequency) that each of them consists of several homogeneous cores. Due to the heterogeneity, the values of power consumption, and reliability of the tasks are differentt,...