Sharif Digital Repository

In order to improve the efficiency of atriums, effective parameters in ventilation and acceleration of airflow are numerous. Nevertheless, parameters such as shape and height of atrium, geometry of the inlet and outlets, opening areas and the presence of heat sources in each store play a vital role. In structures higher than one floor, there is no significant airflow in the upper floors and the ventilation of atrium is unpleasant for residents. Air movement in the building is done by buoyancy-driven force and hot air upward movement due to pressure differences.This study attempts to improve the natural ventilation performance with changing mentioned parameters. So for this purpose, 3D... 

In this thesis, we studied the oscillation of neutrino flavors and the measurement of mixing parameters through the detection of cosmic neutrinos at neutrino telescopes. Most of the astrophysical explosions predict the emission of neutrino flux and kilometer-scale detectors are under construction for the observation of these neutrinos. Detection of astrophysical neutrinos opens a new window to understand the neutrino properties and also the properties of astrophysical sources.In this thesis first we review the phenomenology of neutrino flavor oscillation and characteristics of neutrino mass matrix. By introducing a new class of invariants (under general transformation of lepton fields bases)... 

Neutrino flavor oscillations are clear evidence of massive neutrinos. It has been for more than a decade that neutrino physics became one of active topics in the field of particle physics and various experiments started studying the flavor oscillation of neutrinos. Unfortunately, experiments studying the flavor oscillations are only sensitive to the mass square difference, and they are incapable of providing more information about the absolute mass scale of neutrinos. Additionally, sterile neutrinos having non-standard interactions are under vast investigations and studies. Determination of neutrino masses and their effective number is among the most challenging problems by which... 

Today with growth of wireless communications and progress of small and cheap sensors which have capability of communication and calculation, wireless sensor networks are important and useful topic. But due to energy restrictions, efficient use of resources and increasing network lifetime, have been considered as key factors in network design. In this regard, using efficient multicast routing in energy consumption, for an efficient data transmission to specific number of nodes instead of all nodes code updates, information requests, task assignments and etc., is necessary.On the other hand these networks use unlicensed spectrum and suffer from collision due to congestion caused by other... 

According to prediction of ITRS, power consumption and bandwidth of processors' interconnection, will be the most major bottleneck of the System-on- Chips (SoCs) in the future. Therefore, in MultiProcessor System-on-Chip (MPSoC) architectures, the design constraints will be altered from "Computational Constraints" to "Communicational Constraints". There are three kinds of communications in the surface of the chip: Global, median and local. The main difference between global and local connections is that the length of latter one will be changed with technology. In other words, it is scalable like processor's elements while the length of global connections is practically constant. Even though... 

According to power limitation on a chip and the need to simultaneously access high utilization and low power consumption, Multi-Processor System-on-Chip (MPSoC) architectures have been introduced. The major part of power consumption in a network on chip belongs to interconnects. One of the most important issues is to decrease power consumption while maintaining high utilization. The ability of optical interconnects in decreasing power consumption and increasing utilization has introduced a new architecture called optical network on chip. This architecture uses the benefits of optical signals and elements in order to transfer data. In this thesis, we introduce a new architecture with... 

Recently, a new tool in the study of two-dimensional continuous phase transition was provided by Schramm-Loewner evolution. The main part of SLE is a conformal map which relates growth process of a two-dimensional simple curve to one-dimensional motion on the real axis (so-called Loewner driving function). Time evolution of this map and Loewner driving function is connected via the Loewner differential equation. It turns out that for a certain class of stochastic and conformally invariant curves in two dimensions, the driving function shows Brownian motion in one dimension. Strength point of SLE comes from this fact that all the geometrical properties of such curves is described through a... 

Schramm Loewner evolution (SLE) is a one-parameter family of random simple curves in the complex plane introduced by Schramm in 1999 which is believed to describe the scaling limit of a variety of domain interfaces at criticality. This thesis is concerned with statistical properties of watersheds dividing drainage basins. The fractal dimension of this model is 1.22 which is consistent with the known fractal dimension for several important models such as Invasion percolation and minimum spanning trees (MST). We present numerical evidences that in the scaling limit this model are SLE curves with =1.73, being the only known physical example of an
SLE with <2. This lies outside the... 

Nowadays by increasing the number of processing cores in system-on-chip, using networks-on-chip, as an optimized interconnection foundation for transferring data between processing cores is inevitable .Based on this, the necessity of designing and implementing an optimized structure for testing network-on-chip, considering various overheads such as power consumption, latency, bandwidth and area, becomes an important issue in designing network-on-chip. The purpose of this project is to design an optimized structure for testing routers and connecting links in network, which considers power consumption overhead, latency and area overhead on one hand, and fault coverage on the other hand.... 

As the number of processing cores on a single chip continues to grow, the need for a high band width, low power communication structure, will be the most important requirements of next generation chip multiprocessors. Today, a major part of power consumption in multi core architectures belongs to interconnects. Due to these facts, reducing consuming power, as well as supporting high performance, is concerned in these architectures. The concept of “network-on-chip” emerged to improve the performance of CMPs. But now a day, considering the circumstances of power budges, it’s incapable of presenting new strategies to decrease consuming power and delay. However, optical interconnects have the... 

Nowadays, a large proportion of the power consumption in high-performance multi-processor architectures on chip belongs to connections. Reducing power consumption while maintaining high efficiency in these architectures is one of the main concerns. Networks on Chip (NoC) originally were introduced to improve efficiency, but now, given the importance of power, we must provide some solutions to reduce power consumption, and delay in NOCs. Connections in chip can be divided into three categories: global, intermediate and local, while the length of global connections is almost constant in different scales, local connections are scalable. As a result improving efficiency of a small number of... 

Brown and Henneaux showed that asymptotic symmetries of asymptotically form a conformal group in two dimensions [1]. Also they could derive classical central charge of theory. Fourteen years later, Maldacena, conjectured that this Holographic correspondence could be true for a specific theory a simplified chromodynamics in the boundary of ), this holographic theory attracted physicist communitee's attention. Many physicists tried to make this conjecture more precise. It is worth to say that, no example of holographic correspondence has been completely proven, till now, Because of the difficulty of the calculation. However these days we consider Madacena conjectrure in any arbitrary... 

In this thesis, a hardware is designed and implemented for testing the perfoemance of MIMO communication systems in LTE standard using SCM channel model. This hardware can be used for measuring the BER of 2x2 wireless systems. This hardware is the first channel emulator, with hardware implementation which is using SCM channel model and implementation of a similar one has not been reported.In addition to the implementation of the mentioned channel emulator, a new approach is used for implementing a Gaussian variate generator (GVG) which is implemented on both FPGA and ASIC and shows better characteristics in comparison with the works done in the past. ASIC implementation of this part is done... 

With constant increase in the rate of VLSI circuits manufactured in sites separate from the designers and computer architects, global concern regarding the possibility of integration of malware by the manufacturing foundries has arisen. Particularly, one main issue that affects reliability of the chips is modifications or additions with malicious intention,known as Hardware Trojans, which are easily applicable during design and manufacturing phase of chips. There has been an increasing fraud in chip-set manufacturing. Hardware Trojans may leak confidential information outside the chip, to the attacker, may alter the function of circuit, or completely fail a system. Hence search for new... 

With the widespread use of mobile applications, multimedia and telecommunications, speed of execution has become important. The computation-intensive portions of applications, i.e., loops, devote a significant percentage of their implementation time. Thus, in this thesis, a new method is introduced which greatly increases the execution speed of the loops. Loops are often implemented on coarse-grained reconfiguration architecture (CGRAs) for acceleration, which is a promising architecture with high performance and high power efficiency in comparison to FPGA. In this regard, to reduce the execution time of two-level nested loops, if there are several innermost loops, first, we fuse them, then... 

Today's latest technology integrated circuits are manufactured for a wide range of applications. With the constant increase in the usage rate of integrated circuits, designing a high reliable system is of utmost importance. The avoidance of counterfeit components is a major challenge of hardware security and trust. Counterfeit components cause lower performance and reduced life span. They are of great concern to the manufacturers and consumers of electronic systems, impacting the security and reliability of these systems. If these parts end up in critical applications like medical systems, satellites, aerospace, or power plants, the results could be catastrophic. So far, there are different... 

With constant increase in the rate of VLSI circuits manufactured in sites separate from the designers and computer architects, global concern regarding the possibility of integration of malware by the manufacturing foundries has arisen. Particularly, one main issue that affects relability of the chips is modifications or additions with malicious intension, known as Harware Trojans, which are easily applicable during design and manufacturing phase of chip. This study intends to introduce a model based on the scan chain, a method is provided for intellectual property protection. Currently available IP protection solutions are usually limited to protect single FPGA configurations and require...