Sharif Digital Repository

Considering their special features and numerous applications, sensor networks are noticed so much nowadays. A sub-group of these applications is underwater sensor networks, which encounter some challenges like reliable transportation, routing, MAC, positioning, limited bandwidth, high and variable propagation delay, defective underwater channels and low battery capacity. Acoustic technologies are a particular technology which can make strong underwater communications for Civilian and military applications. These networks are used in oceans for environmental monitoring, under sea discovery, unexpected events prevention, ships assisting, tactical monitoring and naval mine detection, but there... 

This paper presents a comparative study of plasticity and fracture behavior of the NiTi/Ag bilayer for the different crystallographic orientations of the substrate. Molecular dynamic (MD) simulation was used to determine the deformation mechanism, dislocation density, plastic energy dissipation and delamination of the NiTi/Ag bilayers near the interface, when NiTi aligned at (1 0 0), (1 1 1), (1 1 0), (3 2 1), (2 1 0) and (2 1 1) faces during the cyclic-nanoindentation test. The Griffith energy balance model was used to estimate the energy release associated with the delamination. The results of the simulation are suggested the dependence of deformation mechanism, energy release rate (Gin),... 

In this paper, an SET and SEU tolerant latch suitable for use in embedded systems called SETUR (Single Event Transient and Upset Robust latch) is presented and evaluated. The SETUR is based on the use of a redundant feedback line and a CMOS delay element to tolerate the effect of the SETs occurring in the input line of the latch as well as SEUs occurring inside the latch. The experimental results show that the probability of an SET resulting in a soft error can be reduced up to 90% by choosing a proper delay value. The soft error rate of the SETUR due to SEUs occurring inside the latch is reduced by 95% while having lower area, power and performance overhead than the previously proposed... 

The ODYSSEY design methodology has been recently introduced as a viable solution to the increasing design complexity problem in the ASICs. It is an object-oriented design methodology which models a system in terms of its constituting objects and their corresponding method calls. Some of these methods are implemented in hardware; others are simply executed by a general purpose processor. One fundamental element of this methodology is a network on chip that implements method invocation for hardware-based method calls. However this network is prone to faults, thus errors on it may result into system failure. In this paper an architectural fault-tolerance enhancement to the ODYSSEY design... 

This paper proposes and evaluates Low-overhead, Reliable Switch (LRS) architecture to enhance the reliability of Network-on-Chips (NoCs). The proposed switch architecture exploits information and hardware redundancies to eliminate retransmission of faulty flits. The LRS architecture creates a redundant copy of each newly received flit and stores the redundant flit in a duplicated flit buffer that is associated with the incoming channel of the flit. Flit buffers in the LRS are equipped with information redundancy to detect probable bit flip errors. When an error is detected in a flit buffer, its duplicated buffer is used to recover the correct value of the flit. In this way, the propagation... 

This paper presents a cost-efficient technique to jointly use circuit- and architecture-level techniques to protect an embedded processor's register file against soft errors. The basic idea behind the proposed technique is robust register caching (RRC), which creates a cache of the most vulnerable registers within the register file in a small and highly robust cache memory built from circuit-level single-event-upset-protected memory cells. To guarantee that the most vulnerable registers are always stored in the robust register cache, the average number of read operations during a register's lifetime is used as a metric to guide the cache replacement policy. A register is vulnerable to soft... 

Molecular dynamics simulation was used to study of mechanical properties of NiTi/Cu bilayer by nanoindentation and tensile testing. A comparison has been made among mechanical properties measured and plastic deformation process at different copper thickness during nanoindnetation and tensile test of the samples. Embedded atom method potentials for describing of inter-Atomic interaction and Nose-Hoover thermostat and barostat are employed in the simulation at 400 K. The results showed that as the copper film thickness decreased, the maximum load and hardness values increased during nanoindetation. Saha and Nix model is used to describe reduced young's modulus behaviour of the bilayer system... 

Molecular dynamics (MD) simulation was used to study of thermal properties of NiTi/Cu. Embedded atom method (EAM) potentials for describing of inter-atomic interaction and Nose-Hoover thermostat and barostat are employed. The melting of the bi-layers was considered by studying the temperature dependence of the cohesive energy and mean square displacement. To highlight the differences between bi-layers with various copper layer thickness, the effect of copper film thickness on thermal properties containing the cohesive energy, melting point, isobaric heat capacity and latent heat of fusion was estimated. The results show that thermal properties of bi-layer systems are higher than that of... 

In this paper, a hierarchical routing protocol for wireless sensor networks is introduced that aims at reducing the energy imbalance among sensor nodes by integrating the distance of the nodes from the base station into clustering policies. Moreover, the proposed routing protocol does not need any centralized support from a certain node which is at odds with aiming to establish a scalable routing protocol. Mobility management is a salient feature of this protocol that guarantees reliable communications between mobile and static nodes. A simulator was developed in the MATLAB environment to evaluate the performance of this protocol. Simulations on two different network configurations are used... 

This paper presents a behavior-based error detection technique called Control Flow Checking using Branch Trace Exceptions for PowerPC processors family (CFCBTE). This technique is based on the branch trace exception feature available in the PowerPC processors family for debugging purposes. This technique traces the target addresses of program branches at run-time and compares them with reference target addresses to detect possible violations caused by transient faults. The reference target addresses are derived by a preprocessor from the source program. To enhance the error detection coverage, three other mechanisms, i.e., Machine Check Exception, System Trap Instructions and Work Load Timer... 

In this Paper, a software-based control flow checking technique called SWTES (Software-based error detection Technique using Encoded Signatures) is presented and evaluated. This technique is processor independent and can be applied to any kind of processors and microcontrollers. To implement this technique, the program is partitioned to a set of blocks and the encoded signatures are assigned during the compile time. In the run-time, the signatures are compared with the expected ones by a monitoring routine. The proposed technique is experimentally evaluated on an ATMEL MCS51 microcontroller using Software Implemented Fault Injection (SWIFI). The results show that this technique detects about... 

In this paper, we propose a very fast and accurate analytical approach to estimate the overall SER and to identify the most vulnerable gates,flip-flops, and paths of a circuit. Using such information, designers can selectively protect the vulnerable parts resulting in lower power and area overheads that are the most important factors in embedded systems. Unlike previous approaches, the proposed approach firstly does not rely on fault injection or fault simulation; secondly it measures the SER for multi cycles of circuit operation; thirdly, the proposed approach accurately computes all three masking factors, namely, logical, electrical, and timing masking; fourthly, the effects of error... 

Workspace of a mechanism is generally defined as the region of space which end-effector of that mechanism can reach. Determination of workspace is an important task in the design of a mechanism. However, for parallel mechanisms, due to the complexity of solving the forward kinematic equations, determination of workspace is much more complicated than for serial mechanisms. In the literature, time-consuming numerical methods, such as point-by-point searching, are usually employed for this purpose. In this paper, an optimization-based algorithm is introduced for the boundary determination of inclusive and constant orientation workspaces of parallel mechanisms. In the proposed algorithm, thanks... 

Motivated by recent laboratory and field observations, this paper reports the first quantitative measurements of the stabilization phase of interfacial instability in a two-layer fluid in surface wave motion. The instability results from the formation of a resonant triad between the surface wave and noise-level sub-harmonic interfacial waves. To exclude the effects of interfacial mixing on the interaction, the experiments were carried out with immiscible fluids. Carrying out a resonant interaction analysis to the third order of nonlinearity using a Lagrangian formulation, we also show for the first time that the three-wave resonance is inherently accompanied by a harmonic four-wave resonant... 

The phenomenon of the hydraulic jump is so complex that despite considerable laboratory and prototype studies, estimation of its main characteristics in a generalized and accurate form is still difficult. The Artificial Neural Network (ANN) approach aims at limiting the needs for costly and time-consuming experiments. In this study, two ANN models, multi-layer perceptron using back propagation algorithm (MLP/BP) and radial basis function using orthogonal least-squares algorithm (RBF/OLS), were used to predict the roller length, sequent depth, and the relative energy loss of the B-jump. Based on a pre-specified range of jump parameters, the input vectors include: upstream bed slope (tan θ),... 

Recently, the trade-off between power consumption and fault tolerance in embedded processors has been highlighted. This paper proposes an approach to reduce dynamic power of conventional high-level fault-tolerant techniques used in the register file of processors, without affecting the effectiveness of the fault-tolerant techniques. The power reduction is based on the reduction of dynamic power of the unaccessed parts of the register file. This approach is applied to three transient fault-tolerant techniques: Single Error Correction (SEC) hamming code, duplication with parity, and Triple Modular Redundancy (TMR). As a case study, this approach is implemented on the register file of an... 

Soft errors caused by particles strike in combinational parts of digital circuits are a major concern in the design of reliable circuits. Several techniques have been presented to protect combinational logic and reduce the overall circuit Soft Error Rate (SER). Such techniques, however, typically come at the cost of significant area and performance overheads. This paper presents a low area and zero-delay overhead method to protect digital circuits' combinational parts against particles strike. This method is made up of a combination of two sub-methods: (1) a SER estimation method based on signal probability, called Estimation by Characterizing Input Patterns (ECIP) and (2) a protection... 

In this paper, we present a scan-chain-based multiple error recovery technique for triple modular redundancy (TMR) systems (SMERTMR). The proposed technique reuses scan-chain flip-flops fabricated for testability purposes to detect and correct faulty modules in the presence of single or multiple transient faults. In the proposed technique, the manifested errors are detected at the modules' outputs, while the latent faults are detected by comparing the internal states of the TMR modules. Upon detection of any mismatch, the faulty modules are located and the state of a fault-free module is copied into the faulty modules. In case of detecting a permanent fault, the system is degraded to a... 

Despite widespread use of SRAM-based reconfigurable devices (SRDs) in mainstream applications, their usage has been very limited in enterprise and safety-critical applications due to SRAM susceptibility to soft errors. Previous mitigation techniques to protect SRDs impose significant area and power overheads. Additionally, they suffer from susceptibility of configuration bits to multiple bit upsets (MBUs). In this paper, we present a highly available fault-tolerant architecture to protect SRD-based designs against MBUs in both configuration and user bits. In the proposed architecture, the entire design is duplicated with respect to the relative locations of logic blocks within the SRD and... 

This paper proposes an efficient concurrent error detection method using control flow checking for embedded processors. The proposed method is based on the co-operation of two hardware modules: 1) an on-chip hardware component to detect branch instructions and generate signatures for the running program, and 2) an external watchdog processor to compare runtime signatures and branch addresses with the information extracted offline. The proposed method is implemented on an embedded processor core and is evaluated by a simulation based statistical fault injection approach where faults are injected into cache and main memory. Experimental results show that the proposed method detects more than...