Sharif Digital Repository

In nanometer-scale process technologies, the effects of process variations are observed in Multiprocessor System-on-Chips (MPSoC) in terms of variations in frequencies and leakage powers among the processors on the same chip as well as across different chips of the same design. Traditionally, worst-case values are assumed for these parameters and then a deterministic optimization technique is applied to the MPSoC application under design. We show that such worst-case-based approaches are not optimal with the increasing variation observed at system-level, and instead, statistical approaches should be employed. We consider the problem of simultaneously choosing MPSoC architecture and task... 

Titanium anodes coated with noble metal oxides are widely used in chlorate industry. In fact, these anodes are dimensionally stable. In this article, the electrochemical characteristics of the ternary oxide coating created by sol-gel on titanium, which consisted of Ti, Ru and Ir, were investigated in the number of different layers. The electrochemical properties of anodes, morphology of samples, and phase analysis were investigated respectively by cyclic voltammetry and polarization measurements, Field Emission Scanning Electron Microscope (FESEM) and XRD. The result indicated that the application of the more layer number increases the rate of chlorine evolution. Also, The morphology of the... 

Titanium anodes activated by noble metal oxides possess a wide range of advantages and applications. Actually, coating of titanium anodes by highly conductive oxides of noble metals (Ru, Ir) dramatically increases the lifetime of these anodes. In this study, the binary coating consisting of Ti and Ru and the ternary coating consisting of Ti, Ru and Ir were prepared through sol–gel method. After coating of the titanium substrate, the corrosion behavior of coatings was studied by anodic polarization and cyclic voltammetry tests. The lifetime of anodes was determined using accelerated corrosion test. The morphology of coatings was examined by field emission scanning electron microscopy and... 

A model-based algorithm is proposed and tested using the simulator and operation data of a plastic pipeline prototype to locate multiple non-simultaneous leaks in the pipeline. A combination of an extended Kalman filter and obtained relations from the steady state response is used in order to tackle the problem of multi-leak localization. To achieve the mentioned relations, a real pipe with two leaks is equated to a virtual pipe with a single virtual equivalent leak  

Size and number of high-performance data centers are rapidly growing all around the world in recent years. The growth in the leakage power consumption of servers along with its exponential dependence on the ever increasing process variation in nanometer technologies has made it inevitable to move toward variation-aware power reduction strategies in data centers. In this paper, we address the problem of joint server placement and chassis consolidation to minimize power consumption of high-performance computing data centers under process variation. To this end, we introduce two variation-aware server placement heuristics as well as an integer linear programming (ILP)-based server placement... 

Size and number of data centers are fast growing all over the world and their increasing total power consumption is a worldwide concern. Moreover, increase in the amount of process variation in nanometer technologies and its effect on total power consumption of servers has made it inevitable to move toward variation-aware power reduction strategies. This paper formulates a variation-aware joint server placement and task assignment method using Integer Linear Programming (ILP) to minimize total power consumption of data centers. We first determine the optimum placement of servers in the data center racks based on total power consumption of each server and the data center recirculation model... 

The growth in number of data centers and its power consumption costs in recent years, along with ever increasing process variation in nanometer technologies emphasizes the need to incorporate variation-aware power reduction strategies in early design stages. Moreover, since the power characteristics of identically manufactured servers vary in the presence of process variation, their position in the data center should be optimally determined. In this paper, we introduce two heuristic variation-aware server placement algorithm based on power characteristic of servers and heat recirculation model of data center. In the next step, we utilize an Integer Linear Programming (ILP) based... 

In recent years, Android is widely used in cell phones. Dalvik is the virtual machine which is embedded inside the Android operating system, and executes the Android-based applications. Thus, improving efficiency of the Dalvik virtual machine plays an important role in optimizing performance of android-based mobile phones. In this paper, we present a comprehensive analysis of the Dalvik bytecodes and their frequency of use in common Android applications and use the results to determine the most frequently used bytecodes in Dalvik virtual machine to identify best targets for improvement. Our analysis showed that over 82% of total execution time of our Android benchmarks is spent by only 5... 

Leakage power has already become the major contributor to the total on-chip power consumption, rendering its estimation a necessary step in the IC design flow. The problem is further exacerbated with the increasing uncertainty in the manufacturing process known as process variability. We develop a method to estimate the variation of leakage power in the presence of both intra-die and inter-die process variability. Various complicating issues of leakage prediction such as spatial correlation of process parameters, the effect of different input states of gates on the leakage, and DIBL and stack effects are taken into account while we model the simultaneous variability of the two most critical... 

Leakage power has already become the major contributor to the total on-chip power consumption, rendering its estimation a necessary step in the IC design flow. The problem is further exacerbated with the increasing uncertainty in the manufacturing process known as process variability. We develop a method to estimate the variation of leakage power in the presence of both intra-die and inter-die process variability. Various complicating issues of leakage prediction such as spatial correlation of process parameters, the effect of different input states of gates on the leakage, and DIBL and stack effects are taken into account while we model the simultaneous variability of the two most critical... 

MapReduce and its open source implementation, Hadoop, are the prevailing platforms for big data processing. MapReduce is a simple programming model for performing large computational problems in large-scale distributed systems. This model consists of two major phases: Map and Reduce. Between these two main phases, partitioner part is embedded which distributes produced keys by Map tasks among Reduce tasks. When the amount of keys and their associated values, which are called intermediate data, is huge, this part has significant impact on execution time of Reduce tasks, and consequently, completion time of jobs. In this paper, we present a network and resource aware key partitioner to... 

Engines that extract energy from low-grade heat sources, e.g., from other processes, have received considerable attention recently. The use of Fluidyne, which is a liquid piston Stirling engine, is quite popular. Herein, we explore the use of liquid-to-vapor phase change in a Fluidyne. This provides two considerable differentiators; (1) exploitation of very low temperature difference ΔT≈30 K, and (2) relatively low temperature ΔT≈330 K heat sources, for producing mechanical work, and thus electrical energy. The influence of three operating parameters, i.e., input heat flux, working fluid, and filling ratio, on the performance of the engine was characterized. Their optimum values, which yield... 

In this paper, we present a JPEG decoder implemented in our ODYSSEY design methodology. We start with an object-oriented JPEG decoder model. The total operation from modeling to implementation is done automatically by our EDA tool-set in about 10 hours. The resultant system is a JPEG decoder ASIP whose hardware part is implemented on FPGA logic blocks and software part runs on a MicroBlaze processor. This ASIP can be extended by software routines to implement the motion JPEG or MPEG2 decoding algorithms. We implemented our system on ML402 FPGA-based prototype board. Experimental results show that our ASIP implementation is comparable to other approaches while our approach enables quick and... 

Background: Once aligned, long-reads can be a useful source of information to identify the type and position of structural variations. However, due to the high sequencing error of long reads, long-read structural variation detection methods are far from precise in low-coverage cases. To be accurate, they need to use high-coverage data, which in turn, results in an extremely time-consuming pipeline, especially in the alignment phase. Therefore, it is of utmost importance to have a structural variation calling pipeline which is both fast and precise for low-coverage data. Results: In this paper, we present SVNN, a fast yet accurate, structural variation calling pipeline for PacBio long-reads... 

The growing complexity of today's embedded systems demands new methodologies and tools to manage the problems of analysis, design, implementation, and validation of complex-embedded systems. Focusing on this issue, this paper describes a design and implementation toolset using our ODYSSEY methodology, which advocates object-oriented (OO) modeling of embedded systems and its ASIP-based implementation. The proposed approach promotes a smooth transition from high-level object-oriented specification to the final embedded system, which is composed of hardware and software components. The transition from higher to lower abstraction levels is facilitated by the use of our GUI, which supports the... 

A table-based application-specific data prefetching mechanism is presented in this paper. This mechanism is proposed to improve the performance of the application specific instruction-set processors (ASIP) we develop customized to an object-oriented application. In this approach, we divide the data accesses of a class method into two conditional and unconditional parts. We supply the prefetch engine with the static information about each part to prefetch all data fields of an object required by a class method when the class method is invoked. Effective management of memory access patterns by dividing them based on the method to which they belong and storing the access information of nested... 

Background: Once aligned, long-reads can be a useful source of information to identify the type and position of structural variations. However, due to the high sequencing error of long reads, long-read structural variation detection methods are far from precise in low-coverage cases. To be accurate, they need to use high-coverage data, which in turn, results in an extremely time-consuming pipeline, especially in the alignment phase. Therefore, it is of utmost importance to have a structural variation calling pipeline which is both fast and precise for low-coverage data. Results: In this paper, we present SVNN, a fast yet accurate, structural variation calling pipeline for PacBio long-reads... 

Single-rate synchronous digital hierarchy (SDH) networks contain one master block and several slave blocks and the slaves will synchronize themselves by the master clock frequency. However, the clock frequencies of master and slaves are different in multi-rate SDH networks and hence, the slaves require a synchronization circuit to match their clock frequencies with the master clock frequency. This research presents an efficient synchronization circuit for such networks. The proposed circuit occupies smaller area than the prior circuit and requires no clock alignment for its implementation. The circuit constraints are described and the maximum clock frequencies of master and slaves are... 

A wide range of scheduling algorithms used in the data centers have traditionally concentrated on enhancement of performance metrics. Recently, with the rapid growth of data centers in terms of both size and number, the power consumption has become a major challenge for both industry and society. At the software level, energy-aware task scheduling is an effective technique for power reduction in the data centers. However, most of the currently proposed energy-aware scheduling approaches are only paying attention to computation cost. In the other words, they ignore the energy consumed by the network equipment, namely communication cost. In this paper, the problem of scheduling... 

Latency-insensitive design (LID) is a correct by-construction methodology for system on chip design that prevents multiple iterations in synchronous system design. However, one problem in the LID is system throughput reduction. In this study, a protocol is proposed to increase the throughput of internal cores in the latency-insensitive systems when there are several repetitive structures. The validation of the protocol is checked for latency equivalency in various system graphs. A shell wrapper to implement the protocol is described and superimposed logic gates for the shell wrapper are formulated. Simulation is performed for 12 randomly generated systems and four actual systems. The...