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The ODYSSEY methodology takes an unconventional approach to designing at Electronic System Level (ESL): it expands the traditional definition of the processor instruction-set and introduces a new class of processors whose instructions correspond to the methods of an object oriented class library. These new processors, called Object-Oriented Application-Specific Instruction Processor (OO-ASIP), provide a versatile vehicle to explore the synergy between hardware and software not only when implementing an OO application for the first time, but also more significantly, when expanding an existing product for additional functionality or customization. This book provides ESL researchers and... 

We describe implementation of design automation tools that we have developed to automate system-level design using our ODYSSEY methodology, which advocates object-oriented (OO) modeling of the embedded system and ASIP-based implementation of it. Two flows are automated: one synthesizes an ASIP from a given C++ class library, and the other one compiles a given C++ application to run on the ASIP that corresponds to the class library used in the application. This corresponds, respectively, to hardware- and software-generation for the embedded system while hardware-software interface is also automatically synthesized. This implementation also demonstrates three other advantages: firstly, the... 

A huge amount of energy consumption, the cost of this usage and environmental effects have become serious issues for commercial cloud providers. Solar energy is a promising clean energy source, to provide some portion of the Internet data center's (IDC's) energy usage which can reduce environmental effects and total energy costs. Moreover, due to the high energy consumption of the cooling system, considering cooling power in job scheduling can provide efficient solutions to reduce total energy consumption. In this article, we investigate the problem of minimizing the energy cost of an IDC and propose an algorithm which schedules heterogeneous IDC workloads, by considering available renewable... 

Single-rate synchronous digital hierarchy (SDH) networks contain one master block and several slave blocks and the slaves will synchronize themselves by the master clock frequency. However, the clock frequencies of master and slaves are different in multi-rate SDH networks and hence, the slaves require a synchronization circuit to match their clock frequencies with the master clock frequency. This research presents an efficient synchronization circuit for such networks. The proposed circuit occupies smaller area than the prior circuit and requires no clock alignment for its implementation. The circuit constraints are described and the maximum clock frequencies of master and slaves are... 

Latency-insensitive design (LID) is a correct by-construction methodology for system on chip design that prevents multiple iterations in synchronous system design. However, one problem in the LID is system throughput reduction. In this study, a protocol is proposed to increase the throughput of internal cores in the latency-insensitive systems when there are several repetitive structures. The validation of the protocol is checked for latency equivalency in various system graphs. A shell wrapper to implement the protocol is described and superimposed logic gates for the shell wrapper are formulated. Simulation is performed for 12 randomly generated systems and four actual systems. The... 

Communication wire delay between multiple blocks is becoming a critical issue in System on Chip (SoC) design. Scheduling-based Latency-Insensitive Design (LID) is a method to alleviate wire delays by utilizing a central scheduling scheme for periodic clock gating of the blocks. The scheduling scheme resides in shift registers as sequences of '1' and '0' bits. In many systems, these sequences are too long, and have large area overhead. This problem indisposes the implementation of the scheduling based protocol. This paper proposes an algorithm that finds sequences with shorter lengths in comparison with the prior algorithm. On synthetic/random test cases, the algorithm gives 45% reduction on... 

Delay in communication wires causes design iterations in system-on-chip. Latency-insensitive design copes with this issue by encapsulating each core in a shell wrapper and inserting buffers in the wires to separate the design of core from that of communication wires. Scheduling-based latency-insensitive protocol is a methodology which employs shift registers for periodic clock gating of blocks instead of the shell wrappers. In many cases, the bit sequences inside the shift registers are too long and therefore consume a large area. This study presents a heuristic algorithm that optimises the bit sequences and produces them with shorter lengths compared with the existing method. The algorithm... 

The widespread growth of Big Data and the evolution of Internet of Things (IoT) technologies enable cities to obtain valuable intelligence from a large amount of real-time produced data. In a Smart City, various IoT devices generate streams of data continuously which need to be analyzed within a short period of time; using some Big Data technique. Distributed stream processing frameworks (DSPFs) have the capacity to handle real-time data processing for Smart Cities. In this paper, we examine the applicability of employing distributed stream processing frameworks at the data processing layer of Smart City and appraising the current state of their adoption and maturity among the IoT... 

The Network-on-Chip (NoC) paradigm brings networks inside chips. We use the routing capabilities inside NoC to serve as a replacement for Virtual Method Table (VMT) for Object-Oriented (OO) designed hardware/software co-design systems where some methods could be implemented as hardware modules. This eliminates VMT area and performance overhead in OO co-designed embedded systems where resources are limited and where some functionality needs to be implemented in hardware to meet performance goals of the system. Our experimental results on real world embedded applications show up to 32.15% lower area and up to 5.1% higher speed compared to traditional implementation using VMT. © 2007 Elsevier... 

A reconfigurable cache architecture for object-oriented application-specific instruction set processors (ASIP) is presented in this paper. The embedded ASIPs we follow in this research are specifically designed to suit object-oriented applications and are synthesized form an object-oriented highlevel specification. The ASIPs are composed of a processor core along with a number of hardware functional units. In order to support concurrent execution of the functional units, we propose a cache architecture which is virtually divided into a number of partitions. The partition sizes can be dynamically changed depending on the run-time behavior of the application. Partitioning the cache not only... 

In this paper, we present an MPEG-2 video decoder implemented in our ODYSSEY design methodology. We start with an ASIP tailored to the JPEG decompression algorithm. We extend that ASIP by required software routines such that the extended ASIP can now perform MPEG2 decoding while still benefiting from hardware units common between JPEG and MPEG2. This demonstrates the ability of our approach in extending an already manufactured ASIP, which was tailored to a given application, such that it implements new, yet related applications. The implementation platform is a VirtexII-Pro FPGA. The hardware part is implemented in VHDL, and the software runs on a PowerPC processor. Experimental results show... 

We present an embedded-system design flow, discuss its details, and demonstrate its advantages. We adopt the object-oriented methodology for the system-level model because software dominates hardware in embedded systems and the object-oriented methodology is already established for software design and reuse. As the building-block of system implementation, we synthesise application-specific processors that are reusable, through programming, for several related applications. This addresses the high cost and risk of manufacturing specialised hardware tailored to only a single application. Both the processor and its software are generated from the model of the system by the synthesis and... 

At any point in time in an object-oriented (OO) program, a class method is running whose set of unconditionally-accessed data fields can be statically determined. We propose to fetch this set prior to or during the method execution to increase the data cache hit-ratio. This requires that either the software directs the processor cache controller, or the processor is aware of the currently running class method. We follow the latter approach by extending our previous work where we introduced the object-oriented application-specific instruction processor (OO-ASIP) as a processor whose instruction-set consist of methods of a class library. Such an OO-ASIP is aware of the currently running method... 

We unify virtual-method despatch (polymorphism implementation) and network packet-routing operations; virtual-method calls correspond to network packets, and network addresses are allocated such that routing the packet corresponds to dispatching the call. As the run-time routing structure is inherent in Network-on-Chip platforms, this unification implements polymorphism/or free.1  

Energy reduction in embedded processors is a must since most embedded systems run on batteries and processor energy reduction helps increase usage time before needing a recharge. Register files are among the most power consuming parts of a processor core. Register file power consumption mainly depends on its size (height as well as width), especially in newer technologies where leakage power is increasing. We provide a register file architecture that, depending on the application behavior, dynamically (i) adapts the width of individual registers, and (ii) puts partitions of temporarily unused registers into low-power mode, so as to save both static and dynamic power. We show that our scheme... 

MapReduce and its open source implementation, Hadoop, are the prevailing platforms for big data processing. MapReduce is a simple programming model for performing large computational problems in large-scale distributed systems. This model consists of two major phases: Map and Reduce. Between these two main phases, partitioner part is embedded which distributes produced keys by Map tasks among Reduce tasks. When the amount of keys and their associated values, which are called intermediate data, is huge, this part has significant impact on execution time of Reduce tasks, and consequently, completion time of jobs. In this paper, we present a network and resource aware key partitioner to... 

Design technology is expected to rise to electronic system-level (ESL). This necessitates new techniques and tools for synthesizing ESL designs and for verifying them before and after ESL synthesis. A promising verification strategy for future very complex designs is to initially verify the design at the highest level of abstraction, and then check the equivalence of the lower level automatically generated models against that initial golden model. We present one such approach to simulation-based functional verification implemented in our ESL design methodology called ODYSSEY. Our ESL synthesis tool generates a transaction-level model (TLM) at TLM level 2 (i.e., design with partial timing)... 

In this paper, we present a JPEG decoder implemented in our ODYSSEY design methodology. We start with an object-oriented JPEG decoder model. The total operation from modeling to implementation is done automatically by our EDA tool-set in about 10 hours. The resultant system is a JPEG decoder ASIP whose hardware part is implemented on FPGA logic blocks and software part runs on a MicroBlaze processor. This ASIP can be extended by software routines to implement the motion JPEG or MPEG2 decoding algorithms. We implemented our system on ML402 FPGA-based prototype board. Experimental results show that our ASIP implementation is comparable to other approaches while our approach enables quick and... 

The growing complexity of today's embedded systems demands new methodologies and tools to manage the problems of analysis, design, implementation, and validation of complex-embedded systems. Focusing on this issue, this paper describes a design and implementation toolset using our ODYSSEY methodology, which advocates object-oriented (OO) modeling of embedded systems and its ASIP-based implementation. The proposed approach promotes a smooth transition from high-level object-oriented specification to the final embedded system, which is composed of hardware and software components. The transition from higher to lower abstraction levels is facilitated by the use of our GUI, which supports the... 

In the most popular distributed stream processing frameworks (DSPFs), programs are modeled as a directed acyclic graph. Using this model, a DSPF can benefit from the parallelism capabilities of distributed clusters. Choosing a reasonable number of vertices for each operator and mapping the vertices to the appropriate processing resources significantly affect the overall system performance. Due to the simplicity of the current DSPF schedulers, these frameworks perform poorly on large-scale clusters. In this paper, we present a heterogeneity-aware scheduling algorithm that finds the proper number of the vertices of an application graph and maps them to the most suitable cluster node. We begin...