Sharif Digital Repository

In the upward trend of advancing technologies in chips manufacturing, utilizing Network on Chip (NOC) solutions is a sensible approach towards overcoming challenges in System on Chip (SOC). The most common form of NOC is the Wired NOC. The continuous physical size reduction of electronic circuits has led to bandwidth deficiency as well as increased temperature in various parts of these circuits. The vast advancement in chips manufacturing industry has made it possible to embed and adapt telecommunication equipment into chips, giving rise to Wireless NOC (WNOC) manufacturing. However, wireless communication increases fault rate; thereby, the system becomes more vulnerable against transient... 

In the Pay-TV industry, it is necessary to limit access of unauthorized users. Conditional Access System (CAS) is the solution. In the Pay-TV, the ability of instant join and leave operation is desirable for users. On the other hand, this characteristic is in contradiction with growth of user number.
Previous proposed conditional access systems address the requirement of pay-TV from several aspects. Key distribution management is on of them which plays a key role in the security and efficiency of a conditional access system. Re-examining the process of key distribution management make it possible to find a way to provide a greater flexibility for the users.
The purpose of this... 

Today, global on-chip communications become a critical power bottle-neck in high-performance many-core architectures. The importance of power dissipation in NoCs along with power reduction capability of on-chip optical interconnects offers optical network-onchip (ONoC) as a novel technology solution which can introduce on-chip interconnection architecture with high transmission capacity and low power consumption. However, the basic elements that are used in ONoCs are very temperature-sensitive. This may lead to changes in their physical characteristics which will cause incorrectness in network’s functionality. In this thesis, we propose an approach that even the elements change physically... 

Network-on-Chip has been introduced as an effective and scalable communication infrastructure for multiprocessor systems. Nowadays, different applications with various traffic patterns and timing demands must be executed on these platforms. However, static NoCs only perform well for specific domain of applications. Therefore, for different applications, parameters of the system should be designed for the worst case scenario that is considered to be executed on it, or for each domain of application, a chip should be fabricated. The first solution leads to underutilization of system resources and the second one imposes cost of refabricating. Consequently, designers have offered different... 

Nowadays, the use of redundancy components on chips is the best method for replacing defective components on chip. This method improves yield parameter and thus reduces the manufacturing cost of a chip. However, in most of yield improvement methods, redundancy is used when the main components of a chip are defective, which is called cold redundancy. In this project, the manufacturing cost and yield parameters of chips, when using hot redundancy in SIMT processors is investigated. In the case of occurring defect on the chip, the hot redundant components are used for improving yield. Otherwise, they are used in order to improve the performance of chip. In this project, we examine systems,... 

Mixed-criticality embedded systems, as the next-generation of safety-critical systems, are increasingly employed in industry due to consolidating functionalities with varying criticality levels onto the same computing platform. Also, cost reduction and performance improvement encourage adoption of multicore platforms in these systems. Technology scaling, battery-supplied design and heavy computation in mixed-criticality systems necessitates employing energy management techniques. Due to the degrading effects of these techniques on the system’s reliability, reducing energy consumption without sacrificing the reliability requirement is a vital challenge in mixed-criticality systems, in... 

The advancement of Cyber-physical Systems (CPSs) has attracted attention to Mixed-Criticality Systems (MCSs), both in research and industrial designs. Mixed-criticality systems (MCSs) integrate different types of functionalities with varying levels of criticality onto the shared computing platform. The scheduling algorithms for MCSs must guarantee that all high criticality tasks are completed by their deadlines in different operation modes of the system. In addition to certification, as multi-core platforms are becoming a dominant trend in designing MCSs, simultaneous energy and reliability management, and Quality of Service (QoS) are other significant challenges in designing MCSs. Indeed,... 

Deep neural networks, as one of the main approaches in machine learning, play a crucial role in analyzing complex data and identifying hidden patterns. However, significant challenges such as high sensitivity to input errors, noise, and minor data variations still persist. One of the key strategies to address these challenges and improve the stability and accuracy of neural networks is the proper and optimal use of activation functions. Activation functions allow networks to process data non-linearly and extract more complex features from the data. However, an incorrect choice of activation function or suboptimal tuning can reduce the network's performance and make it more sensitive to input... 

Combining the concept of Network-on-Chip (NoC) with three dimensional integrated circuits technology on 3D NoC enables reduction of propagation delay, interconnect power consumption, and die area, as well as increase in system operational bandwidth. Nevertheless, reducing the feature size of semiconductor technologies has raised certain aging mechanisms, like Negative Bias Temperature Instability (NBTI) and Electromigration, as the main reasons for reduction in reliability and lifetime of NoCs. Reduction in die area results in an increase in power density of the chip, which exacerbates temperature-related concerns of 3D NoCs compared to 2D NoCs. Thus, the aging mechanisms that are directly... 

According to prediction of ITRS, power consumption and bandwidth of processors' interconnection, will be the most major bottleneck of the System-on- Chips (SoCs) in the future. Therefore, in MultiProcessor System-on-Chip (MPSoC) architectures, the design constraints will be altered from "Computational Constraints" to "Communicational Constraints". There are three kinds of communications in the surface of the chip: Global, median and local. The main difference between global and local connections is that the length of latter one will be changed with technology. In other words, it is scalable like processor's elements while the length of global connections is practically constant. Even though... 

Nowadays, a large proportion of the power consumption in high-performance multi-processor architectures on chip belongs to connections. Reducing power consumption while maintaining high efficiency in these architectures is one of the main concerns. Networks on Chip (NoC) originally were introduced to improve efficiency, but now, given the importance of power, we must provide some solutions to reduce power consumption, and delay in NOCs. Connections in chip can be divided into three categories: global, intermediate and local, while the length of global connections is almost constant in different scales, local connections are scalable. As a result improving efficiency of a small number of... 

According to power limitation on a chip and the need to simultaneously access high utilization and low power consumption, Multi-Processor System-on-Chip (MPSoC) architectures have been introduced. The major part of power consumption in a network on chip belongs to interconnects. One of the most important issues is to decrease power consumption while maintaining high utilization. The ability of optical interconnects in decreasing power consumption and increasing utilization has introduced a new architecture called optical network on chip. This architecture uses the benefits of optical signals and elements in order to transfer data. In this thesis, we introduce a new architecture with... 

As the number of processing cores on a single chip continues to grow, the need for a high band width, low power communication structure, will be the most important requirements of next generation chip multiprocessors. Today, a major part of power consumption in multi core architectures belongs to interconnects. Due to these facts, reducing consuming power, as well as supporting high performance, is concerned in these architectures. The concept of “network-on-chip” emerged to improve the performance of CMPs. But now a day, considering the circumstances of power budges, it’s incapable of presenting new strategies to decrease consuming power and delay. However, optical interconnects have the... 

With constant increase in the rate of VLSI circuits manufactured in sites separate from the designers and computer architects, global concern regarding the possibility of integration of malware by the manufacturing foundries has arisen. Particularly, one main issue that affects reliability of the chips is modifications or additions with malicious intention,known as Hardware Trojans, which are easily applicable during design and manufacturing phase of chips. There has been an increasing fraud in chip-set manufacturing. Hardware Trojans may leak confidential information outside the chip, to the attacker, may alter the function of circuit, or completely fail a system. Hence search for new... 

Today's latest technology integrated circuits are manufactured for a wide range of applications. With the constant increase in the usage rate of integrated circuits, designing a high reliable system is of utmost importance. The avoidance of counterfeit components is a major challenge of hardware security and trust. Counterfeit components cause lower performance and reduced life span. They are of great concern to the manufacturers and consumers of electronic systems, impacting the security and reliability of these systems. If these parts end up in critical applications like medical systems, satellites, aerospace, or power plants, the results could be catastrophic. So far, there are different... 

With constant increase in the rate of VLSI circuits manufactured in sites separate from the designers and computer architects, global concern regarding the possibility of integration of malware by the manufacturing foundries has arisen. Particularly, one main issue that affects relability of the chips is modifications or additions with malicious intension, known as Harware Trojans, which are easily applicable during design and manufacturing phase of chip. This study intends to introduce a model based on the scan chain, a method is provided for intellectual property protection. Currently available IP protection solutions are usually limited to protect single FPGA configurations and require... 

Nowadays integrated circuits are extremely vulnerable to hardware trojans (HT). Hardware trojans can be injected into the ICs in design or fabricate phase, and damage system’s functionality or security. In this thesis, we first describe hardware trojan definition, classification and types of HTs, negative effects, detection ways and analysis of them. Then we propose a new solution in order to solve the negative points of previous methods  

With the widespread use of mobile applications, multimedia and telecommunications, speed of execution has become important. The computation-intensive portions of applications, i.e., loops, devote a significant percentage of their implementation time. Thus, in this thesis, a new method is introduced which greatly increases the execution speed of the loops. Loops are often implemented on coarse-grained reconfiguration architecture (CGRAs) for acceleration, which is a promising architecture with high performance and high power efficiency in comparison to FPGA. In this regard, to reduce the execution time of two-level nested loops, if there are several innermost loops, first, we fuse them, then... 

Integrating functionalities of different-criticality levels on a shared computing platform known as Mixed-Criticality Systems (MCSs) has been noticed recently in research and industrial designs. Due to the battery-operated nature of some MCSs and different reliability requirement for tasks, joint energy and reliability management is crucial in these systems. Another important issue in these systems which is rarely addressed in previous works is tolerating permanent faults. In this thesis, we propose two comprehensive schemes: MC-4S and MC-2S which guarantee to tolerate permanent faults and maintaining the system reliability with respect to the transient faults. In addition, guaranteeing the... 

In recent years, GPUs are becoming ideal candidates for processing a variety of high performance applications. By relying on thousands of concurrent threads in applications and the computational power of large numbers of computing units, GPGPUs have provided high efficiency and throughput. To achieve the potential computational power of GPGPUs in broader types of applications, we need to apply some modifications. By understanding the features and properties of applications, we can execute them in a more proper way on GPUs. Therefore, considering applications’ behavior, we define 5 different categories for them. Every category has special definitions, and we change the configuration of GPU...