Modeling and active control of chatter vibrations of piezoelectric stacked machining arm in micro-turning process

, Article Meccanica ; Volume 55, Issue 9 , 18 July , 2020 , Pages 1707-1731 Hesabi Hesari, A ; Moradi, H ; Movahhedy, M. R ; Sharif University of Technology

Springer 2020

Abstract

Self-excited vibrations known as chatter are considered as the most detrimental issue in micro-turning processes. Occurring unpredictably, they adversely affect the tool life, productivity rate and surface quality of the machining processes. In this paper, a novel machining arm is modeled as a piezoelectric stacked rod which is subjected to a chatter force in the orthogonal micro-turning process. Due to the fact that machining processes are affected by various sources of uncertainties, H∞ robust control approach is used to suppress the chatter vibrations of the machining arm in the presence of tool wear and dynamic model parameter variations. Also, input control force of the system is...

Robust Control of Self-Excited Vibration in Machining Arm

, M.Sc. Thesis Sharif University of Technology Hesabi Hesari, Abbas (Author) ; Moradi, Hamed (Supervisor) ; Movahhedi, Mohammad Reza (Supervisor)

Abstract

Nowadays, applications of industrial robots are significantly increasing due to their flexibility, programmable, accuracy, rapidity and etc. Among these, machining robots play an important role at manufacturing industries. One of the main concerns of the researchers, is the tip vibrations of robot arms. In most times, these vibrations are self-excited, unpredictable and intolerable. Thus, finding a method for reducing vibration should be investigated. The purpose of vibration control is vibration suppression to enhance the reliability of the system. The aim of this project is the modeling of the machining robot arm in turning process and then application of robust control to reduce...

Towards a general framework for evaluating software development methodologies

, Article Proceedings - International Computer Software and Applications Conference, 19 July 2010 through 23 July 2020 ; July , 2010 , Pages 208-217 ; 07303157 (ISSN) ; 9780769540856 (ISBN) Hesari, S ; Mashayekhi, H ; Ramsin, R ; Sharif University of Technology

2010

Abstract

It has become essential to scrutinize and evaluate software development methodologies, mainly because of their increasing number and variety. Evaluation is required to gain a better understanding of the features, strengths, and weaknesses of the methodologies. The results of such evaluations can be leveraged to identify the methodology most appropriate for a specific context. Moreover, methodology improvement and evolution can be accelerated using these results. However, despite extensive research, there is still a need for a feature/criterion set that is general enough to allow methodologies to be evaluated regardless of their types. We propose a general evaluation framework which addresses...

Chern–Weil Theory Extended to a Class of Infinite Dimensional Bundles

, M.Sc. Thesis Sharif University of Technology Hesari, Abdolaziz (Author) ; Esfahani Zadeh, Mostafa (Supervisor)

Abstract

Given a principal bundle a characteristic class is an element of the cohomology al- gebra of the classifying space of structure group of the bundle with coeﬃcients in a commutative ring with unit ,which have a functorial property .When the structure groupe of the bundle is a Lie group and the coeﬃcient ring is the real or complex num- bers , the Chern–Weil approach provides a geometric construction of char-acteristic classes. Classical Chern–Weil formalism relates geometry to topology, assigning to the cur- vature of a connection, de Rham cohomology classes of the underlying manifold.This theory developped in the 40’s by Shiing-ShenChern and Andre Weil which can be seen as a generalisation...

Hierarchical Optical Network-on-Chip Based on Hypercube Topology

, M.Sc. Thesis Sharif University of Technology Abdollahi, Meisam (Author) ; Hesabi, Shahin (Supervisor)

Abstract

According to prediction of ITRS, power consumption and bandwidth of processors' interconnection, will be the most major bottleneck of the System-on- Chips (SoCs) in the future. Therefore, in MultiProcessor System-on-Chip (MPSoC) architectures, the design constraints will be altered from "Computational Constraints" to "Communicational Constraints". There are three kinds of communications in the surface of the chip: Global, median and local. The main difference between global and local connections is that the length of latter one will be changed with technology. In other words, it is scalable like processor's elements while the length of global connections is practically constant. Even though...

Architecture of Reconfigurable Optical Network-on-Chip

, M.Sc. Thesis Sharif University of Technology Falahati, Hajar (Author) ; Hesabi, Shahin (Supervisor)

Abstract

According to power limitation on a chip and the need to simultaneously access high utilization and low power consumption, Multi-Processor System-on-Chip (MPSoC) architectures have been introduced. The major part of power consumption in a network on chip belongs to interconnects. One of the most important issues is to decrease power consumption while maintaining high utilization. The ability of optical interconnects in decreasing power consumption and increasing utilization has introduced a new architecture called optical network on chip. This architecture uses the benefits of optical signals and elements in order to transfer data. In this thesis, we introduce a new architecture with...

High Speed CDMA Communication in Optical Network on Chip

, M.Sc. Thesis Sharif University of Technology Abdi, Mania (Author) ; Hesabi, Shahin (Supervisor)

Abstract

As the number of processing cores on a single chip continues to grow, the need for a high band width, low power communication structure, will be the most important requirements of next generation chip multiprocessors. Today, a major part of power consumption in multi core architectures belongs to interconnects. Due to these facts, reducing consuming power, as well as supporting high performance, is concerned in these architectures. The concept of “network-on-chip” emerged to improve the performance of CMPs. But now a day, considering the circumstances of power budges, it’s incapable of presenting new strategies to decrease consuming power and delay. However, optical interconnects have the...

Modified WK-Recursive Topology for an Optical Network-on-Chip

, M.Sc. Thesis Sharif University of Technology Mahdavian, Hojjat (Author) ; Hesabi, Shahin (Supervisor)

Abstract

Nowadays, a large proportion of the power consumption in high-performance multi-processor architectures on chip belongs to connections. Reducing power consumption while maintaining high efficiency in these architectures is one of the main concerns. Networks on Chip (NoC) originally were introduced to improve efficiency, but now, given the importance of power, we must provide some solutions to reduce power consumption, and delay in NOCs. Connections in chip can be divided into three categories: global, intermediate and local, while the length of global connections is almost constant in different scales, local connections are scalable. As a result improving efficiency of a small number of...

Hardware Trojan Detection: A Size-Aware Approach

, M.Sc. Thesis Sharif University of Technology Heydarshahi, Behnam (Author) ; Hesabi, Shahin (Supervisor)

Abstract

With constant increase in the rate of VLSI circuits manufactured in sites separate from the designers and computer architects, global concern regarding the possibility of integration of malware by the manufacturing foundries has arisen. Particularly, one main issue that affects reliability of the chips is modifications or additions with malicious intention,known as Hardware Trojans, which are easily applicable during design and manufacturing phase of chips. There has been an increasing fraud in chip-set manufacturing. Hardware Trojans may leak confidential information outside the chip, to the attacker, may alter the function of circuit, or completely fail a system. Hence search for new...

Accelerating Perfect and Imperfect Loops Using Reconfigurable Architectures

, M.Sc. Thesis Sharif University of Technology Tanhaee, Effat (Author) ; Hesabi, Shahin (Supervisor)

Abstract

With the widespread use of mobile applications, multimedia and telecommunications, speed of execution has become important. The computation-intensive portions of applications, i.e., loops, devote a significant percentage of their implementation time. Thus, in this thesis, a new method is introduced which greatly increases the execution speed of the loops. Loops are often implemented on coarse-grained reconfiguration architecture (CGRAs) for acceleration, which is a promising architecture with high performance and high power efficiency in comparison to FPGA. In this regard, to reduce the execution time of two-level nested loops, if there are several innermost loops, first, we fuse them, then...

A Scan Chain-Based Aging Monitoring Scheme for Detection of Recycled Chips

, M.Sc. Thesis Sharif University of Technology Ostovar, Atanaz (Author) ; Hesabi, Shahin (Supervisor)

Abstract

Today's latest technology integrated circuits are manufactured for a wide range of applications. With the constant increase in the usage rate of integrated circuits, designing a high reliable system is of utmost importance. The avoidance of counterfeit components is a major challenge of hardware security and trust. Counterfeit components cause lower performance and reduced life span. They are of great concern to the manufacturers and consumers of electronic systems, impacting the security and reliability of these systems. If these parts end up in critical applications like medical systems, satellites, aerospace, or power plants, the results could be catastrophic. So far, there are different...

A Scheme for Counterfeit Chip Detection Using Scan Chain

, M.Sc. Thesis Sharif University of Technology Hashemi, Mona (Author) ; Hesabi, Shahin (Supervisor)

Abstract

With constant increase in the rate of VLSI circuits manufactured in sites separate from the designers and computer architects, global concern regarding the possibility of integration of malware by the manufacturing foundries has arisen. Particularly, one main issue that affects relability of the chips is modifications or additions with malicious intension, known as Harware Trojans, which are easily applicable during design and manufacturing phase of chip. This study intends to introduce a model based on the scan chain, a method is provided for intellectual property protection. Currently available IP protection solutions are usually limited to protect single FPGA configurations and require...

An Efficient Hardware Trojan Detector Using On-chip Ring Oscillator

, M.Sc. Thesis Sharif University of Technology Khodadadi, Mohsen (Author) ; Hesabi, Shahin (Supervisor)

Abstract

Nowadays integrated circuits are extremely vulnerable to hardware trojans (HT). Hardware trojans can be injected into the ICs in design or fabricate phase, and damage system’s functionality or security. In this thesis, we first describe hardware trojan definition, classification and types of HTs, negative effects, detection ways and analysis of them. Then we propose a new solution in order to solve the negative points of previous methods

Improving Performance of GPGPU Considering Reliability Requirements

, M.Sc. Thesis Sharif University of Technology Motallebi, Maryam (Author) ; Hesabi, Shahin (Supervisor)

Abstract

In recent years, GPUs are becoming ideal candidates for processing a variety of high performance applications. By relying on thousands of concurrent threads in applications and the computational power of large numbers of computing units, GPGPUs have provided high efficiency and throughput. To achieve the potential computational power of GPGPUs in broader types of applications, we need to apply some modifications. By understanding the features and properties of applications, we can execute them in a more proper way on GPUs. Therefore, considering applications’ behavior, we define 5 different categories for them. Every category has special definitions, and we change the configuration of GPU...

Improving Manufacturing Yield and Life Cycle of Special Purpose SIMT Processors for Inexact Computing

, M.Sc. Thesis Sharif University of Technology Afarin, Mahbod (Author) ; Hesabi, Shahin (Supervisor)

Abstract

The downscaling of feature size and higher process variation in COMS nano-technology are anticipated to introduce higher manufacturing anomalies. On the other hand, designs are getting more complicated due to more innovative applications where they need higher numbers of transistors. Because of these issues, integrated circuits manufacturing has become more complicated than before. Complexity in manufacturing process increases the probability of the defects in chips. This phenomenon reduces the fabrication yield. Conventional methods like fault tolerant techniques, defect tolerant techniques and redundancy are not separately good enough for improving manufacturing yield. On the other hand,...

Aging Mitigation for Arithmetic and Logic Unit of a Processor

, M.Sc. Thesis Sharif University of Technology Sharifi, Ferdous (Author) ; Hesabi, Shahin (Supervisor)

Abstract

Shrinking the dimensions of transistors in recent fabrication technologies has led to an increase in the aging rate of chips, as the most important challenge in reliability of new processors. Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) are amongst the most important adverse effect of transistor shrinkage. These two effects decrease the switching speed of transistors by increasing its threshold voltage over time. Threshold voltage shift causes timing violation in combinational parts of circuit and decreases the robustness of sequential parts against soft errors. Between different units of a processor, Arithmetic and Logic Unit (ALU) is one of the most susceptible units...

Reliablity-Aware Energy Management for Mixed-Criticality Systems on Multicores

, M.Sc. Thesis Sharif University of Technology Naghavi, Amin (Author) ; Hesabi, Shahin (Supervisor)

Abstract

Integrating functionalities of different-criticality levels on a shared computing platform known as Mixed-Criticality Systems (MCSs) has been noticed recently in research and industrial designs. Due to the battery-operated nature of some MCSs and different reliability requirement for tasks, joint energy and reliability management is crucial in these systems. Another important issue in these systems which is rarely addressed in previous works is tolerating permanent faults. In this thesis, we propose two comprehensive schemes: MC-4S and MC-2S which guarantee to tolerate permanent faults and maintaining the system reliability with respect to the transient faults. In addition, guaranteeing the...

Advanced nonlinear dynamic analysis of arch dams considering joints effects

, Article Advances in Mechanical Engineering ; Volume 201 , 2014 ; ISSN: 16878132 Hesari, M. A ; Ghaemian, M ; Shamsai, A ; Sharif University of Technology

2014

Abstract

Influence of joints behavior on arch dams operation during the earthquakes is investigated. The case study is the Karun-1 double curvature arch dam with the height of 200 meters. The arch dam-foundation-reservoir systems are modeled with and without joints and estimate the effects of contraction and lift joints on stresses and displacements response histories for assessing the earthquake performance. According to nolinear dynamical analysis results, inclusion of the contraction and lift joints considerably influenced the dam response

A comparative study of two cavitation modeling strategies for simulation of inviscid cavitating flows

, Article Ocean Engineering ; Volume 108 , November , 2015 , Pages 257-275 ; 00298018 (ISSN) Hejranfar, K ; Ezzatneshan, E ; Fattah Hesari, K ; Sharif University of Technology

Elsevier Ltd 2015

Abstract

In the present work, two cavitation modeling strategies, namely the barotropic cavitation model and the transport equation-based model are applied and assessed for the numerical simulation of inviscid cavitating flows over two-dimensional and axisymmetric geometries. The algorithm uses the preconditioned Euler equations employing the interface capturing method for both the cavitation models. A same numerical solution procedure is used herein for discretizing the governing equations resulting from these two cavitation modeling strategies for the assessment to be valid and reliable. A central difference finite-volume scheme employing the suitable dissipation terms to account for density jumps...

Configuration Design of Mechanical Structure Coupled with MSMA in Energy Harvesting

, M.Sc. Thesis Sharif University of Technology Effatpanah Hesari, Mojtaba (Author) ; Sayyadi, Hassan (Supervisor)

Abstract

In recent years, energy harvesting from ambient sources in order to use for low-powered electronics has been considered by many researchers. Wind energy, solar energy, water energy, mechanical energy from vibrations, etc are common sources of ambient energy. In this thesis, optimization of energy harvesting from ambient vibration using magnetic shape memory alloy is presented. To this end, a clamped-clamped beam coupled with MSMA units is considered. A shock load is applied to a proof mass which is attached to the middle of the beam. As a result of beam vibration a longitudinal strain is produced in the MSMA. This strain changes magnetic flux inside the coil connected to MSMA and as a...