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Reducing the size of the technology increases leakage power in Network-on-Chip (NoC) routers drastically. Power-gating, particularly in NoC routers, is one of the most efficient approaches for alleviating the leakage power. Although applying power-gating techniques alleviates NoC power consumption due to high proportion of idleness in NoC routers, since the timing behavior of packets is irregular, even in low injection rates, performance overhead in power-gated routers is significant. In this paper, we present SMART, a Scalable Mapping And Routing Technique, with virtually no area overhead on the network. It improves the irregularity of the timing behavior of packets in order to mitigate... 

Two main sources for power dissipation in parallel buses are data transitions on each wire and coupling between adjacent wires. So far, many techniques have been proposed for reducing the self and coupling powers. Most of these methods utilize one (or more) control bit(s) to manage the behavior of data transitions on the parallel bus. In this paper, we propose a new coding scheme, referred to as GPH, to reduce power dissipation of these control bits. GPH coding scheme employs partitioned Bus Invert and Odd Even Bus-Invert coding techniques. This method benefits from Particle Swarm Optimization (PSO) algorithm to efficiently partition the bus. In order to reduce self and coupling powers of... 

Coping with the intrinsic limitations of electrical networks-on-chip, optical on-chip interconnect is emerged as a promising paradigm for future high performance multi-core designs. However, optical networks-on-chip (ONoCs) are drastically vulnerable to on-chip thermal fluctuation. Specifically, electrical power consumed by processing cores induces temperature drift, which may cause false paths for optical data communication through the network. Therefore, customizing electrical power distribution throughout the chip plays a critical role for reliable data communication in ONoCs. On the other hand, chip-scale distribution of electrical power is directly affected by mapping various... 

We propose a new optical reconfigurable Network-on-Chip (NoC), named ReFaT ONoC (Reconfigurable Flat and Tree Optical NoC). ReFaT is a dynamically reconfigurable architecture, which customizes the topology and routing paths based on the application characteristics. ReFaT, as an all-optical NoC, routes optical packets based on their wavelengths. For this purpose, we propose a novel architecture for the optical switch, which eliminates the need for optical resource reservation, and thus avoids the corresponding latency and area overheads. As a key idea for dynamic reconfiguration, each application is mapped to a specific set of wavelengths and utilizes its dedicated routing algorithm. We... 

Integrated silicon photonic networks have attracted a lot of attention in the recent decades due to their potentials for low-power and high-bandwidth communications. However, these promising networks, as the future technology, are drastically susceptible to thermal fluctuations, which may paralyze wavelength-based operation of these networks. In this regard, precise addressing of thermally induced faults in optical networks-on-chip (ONoCs), as well as revealing practical methods to tackle this challenge will be a break-even point toward implementation of this technology. In this paper, thermal variation is investigated through analyzing on-chip power distribution, which is addressed by power... 

Due to the battery-operated nature of embedded Mixed-Criticality Systems, simultaneous energy and reliability management is a cru-cial issue in designing these systems. We propose two comprehensive schemes, MC-2S and MC-4S, which tolerate permanent faults through exploiting the inherent redundancy of multicore systems for applying standby-sparing technique and maintaining the system re-liability against transient faults with low energy overhead. In these schemes, two copies of each high-criticality task are scheduled on different cores to guarantee their timeliness in case of permanent fault occurrence. In order to guarantee the quality of service of low-criticality tasks, in the MC-2S... 

Two main sources for power dissipation in parallel buses are data transitions on each wire and coupling between adjacent wires. There are many techniques for reducing the transition and coupling powers. These methods utilize extra control bits to manage the behavior of data transitions on parallel bus. In this paper, we propose a new coding scheme which tries to reduce power dissipation of control bits. The proposed method employs partitioned Bus Invert and Odd Even Bus Invert coding techniques. This method benefits from Particle Swarm Optimization (PSO) algorithm to efficiently partition the bus. In order to reduce transition and coupling power of control bits, it finds partitions with... 

Due to the battery-operated nature of some embedded Mixed-Criticality Systems, simultaneous energy and reliability management is a crucial issue in designing these systems. We propose two comprehensive schemes, MC-2S and MC-4S, which exploit the standby-sparing technique to tolerate permanent faults through inherent redundancy of multicore systems and maintain the system's reliability against transient faults with low energy overhead. In these schemes, two copies of each high-criticality task are scheduled on different cores to guarantee their timeliness in case of permanent fault occurrence. To guarantee the quality of service of low-criticality tasks, in the MC-2S scheme, one backup copy... 

This paper proposes a new optical network-on-chip which is scalable, low-power and high-performance. We design a centralized all-optical router which takes advantage of wavelength based structures. Our design achieves fully contention-free operation by utilizing path-based algorithms. By merging primary photonic switches and utilizing WDM technique, we mitigated the number of basic switching elements and thus reduced the consumed power down to 47.37% in comparison with the most prominent structure introduced for wavelength routing; i.e., the λ-Router. We obtained this superiority while maintaining the performance as high as the previous structures, which yields in energy savings. Moreover,... 

As manufacturing processes scale to smaller feature sizes and processors become more complex, it is becoming challenging to have fabricated devices that operate according to their speciication in the irst place: yield losses are mounting [3]. © 2017 ACM  

As manufacturing processes scale to smaller feature sizes and processors become more complex, it is becoming challenging to have fabricated devices that operate according to their speciication in the irst place: yield losses are mounting [3]. In this work, we investigate adding heterogeneous hot redundancy (i.e., the architecture of redundant hot cores is diferent from the baseline cores) to improve the cost and performance of multicore single-instruction, multiple-thread (SIMT) architectures. We propose to utilize x86 out of order (OoO) cores as redundancy in SIMT processors. In this case, dice with unused functional redundancies can beneit from two types of processing cores (OoO and SM)  

Many-cores execute a large number of diverse applications concurrently. Inter-Application interference can lead to a security threat as timing channel attack in the on-chip network. A non-interference communication in the shared on-chip network is a dominant necessity for secure many-core platforms to leverage the concepts of the cloud and embedded system-on-chip. The current non-interference techniques are limited to static scheduling and need router modification at micro-Architecture level. Mapping of applications can effectively determine the interference among applications in on-chip network. In this work, we explore non-interference approaches through run-Time mapping at software and... 

Optical networks-on-chip are introduced as an alternative for electrical interconnects in many-core systems, due to their low delay and power consumptions, as well as their high bandwidths. Despite these advantages, physical characteristics of the photonic components are highly sensitive to thermal variations, which results in optical data misrouting through the optical networks at the presence of temperature fluctuation. In this paper, we propose a thermally-resilient all-optical communication approach which improves reliability, as well as performance of the optical networks. For this purpose, we take advantages of auxiliary waveguides and a novel wavelength assignment approach to avoid... 

With the growing number of cores, high-performance systems face power challenges due to dominating communication power. Thus, attaining energy efficient high-bandwidth inter-core communication nominates photonic network-on chip as the most promising interconnection paradigm. Although photonic networks pave the way for extremely higher performance communications, their intrinsic susceptibility to thermal fluctuations intimidates reliability of system. This necessitates the development of methodologies to analyze and model thermal effects on network behavior. In this paper, we model temperature fluctuations of optical chips and analyze photonic networks in a holistic approach. We present a... 

In this paper, we present results of our experiments in implementation of a widely used DSP primitive on a programmable SoC (System-on-a-Chip) Device. The DSP primitive is a 16-bit digital FIR filter which we implemented on Triscend E5 CSoC® family. Experimental results show that by properly breaking the DSP task into hardware and software parts, one can achieve higher throughput compared to DSP processor implementations, while having more flexibility and less time-to-design compared to full-hardware realizations. Programmable SoC device facilitates rapid design-space exploration, which we employed to optimize our mixed hardware-software architecture. We compared our filter throughput to... 

This paper proposes a novel topology for optical Network on Chip (NoC) architectures with the key advantages of regularity, vertex symmetry, scalability to large scale networks, constant node degree, and simplicity. Moreover, we propose a minimal deterministic routing algorithm for the proposed topology which leads to small and simple photonic routers. Built upon our novel network topology, we present a scalable all-optical NoC, referred to as 2D-HERT, which offers passive routing of optical data streams based on their wavelengths. Utilizing wavelength routing method along with Wavelength Division Multiplexing technique, our proposed optical NoC eliminates the need for electrical resource... 

The paper proposes a scalable wavelength-switched optical NoC, named as SWS-ONoC. The proposed architecture is built upon a novel all-optical router which passively routes optical data streams based on their wavelengths. Utilizing wavelength routing method, SWS-ONoC eliminates electrical transactions for optical resource reservation and hence, reduces latency and area overheads of the electrical units. The proposed architecture benefits from Wavelength Division Multiplexing (WDM) scheme to efficiently route multicast optical packets concurrent with unicast data streams. Performing a series of simulation-based experiments, we study efficiency of the proposed architecture, its power and energy... 

This paper proposes a novel all-optical router as a building block for a scalable wavelength-switched optical NoC. The proposed optical router, named as AOR, performs passive routing of optical data streams based on their wavelengths. Utilizing wavelength routing method, AOR eliminates the need for electrical resource reservation and the corresponding latency and area overheads. Taking advantage of Wavelength Division Multiplexing (WDM) technique, the proposed architecture is capable of data multicasting, concurrent with unicast data transmission, with high bandwidth and low power dissipation, without imposing noticeable area and latency overheads. Comparing AOR against previously proposed... 

As transistor dimensions continue to shrink, long-term reliability threats, such as Negative Bias Temperature Instability, affect multicore processors lifespan. This letter proposes a load balancing technique, based on the rate of integer and floating-point instructions per workloads. This technique classifies workloads into integer-majority and floating-point-majority classes and migrates workloads among cores in order to relax the stressed execution units. The context switching feature of operating system is employed to reduce implementation and performance overheads of the proposed technique. According to the simulations, the proposed technique reduces the aging rate of a multicore... 

In this paper, an infrastructure for debug of complex SoCs that employs assertions is introduced. The proposed infrastructure combines traditional off-chip analysis techniques with on-chip at-speed debug facilities. The main part of on-chip debug hardware consists of data and transaction monitors. The monitor hardware is automatically generated by synthesizing the assertions that were used for verification and validation before manufacturing. We have integrated the proposed method in a system-level design methodology. By synthesizing various assertions from different kinds in a case study we have studied the overhead of our method. © 2007 IEEE