Sharif Digital Repository

Today, global on-chip communications become a critical power bottle-neck in high-performance many-core architectures. The importance of power dissipation in NoCs along with power reduction capability of on-chip optical interconnects offers optical network-onchip (ONoC) as a novel technology solution which can introduce on-chip interconnection architecture with high transmission capacity and low power consumption. However, the basic elements that are used in ONoCs are very temperature-sensitive. This may lead to changes in their physical characteristics which will cause incorrectness in network’s functionality. In this thesis, we propose an approach that even the elements change physically... 

Network-on-Chip has been introduced as an effective and scalable communication infrastructure for multiprocessor systems. Nowadays, different applications with various traffic patterns and timing demands must be executed on these platforms. However, static NoCs only perform well for specific domain of applications. Therefore, for different applications, parameters of the system should be designed for the worst case scenario that is considered to be executed on it, or for each domain of application, a chip should be fabricated. The first solution leads to underutilization of system resources and the second one imposes cost of refabricating. Consequently, designers have offered different... 

Nowadays, the use of redundancy components on chips is the best method for replacing defective components on chip. This method improves yield parameter and thus reduces the manufacturing cost of a chip. However, in most of yield improvement methods, redundancy is used when the main components of a chip are defective, which is called cold redundancy. In this project, the manufacturing cost and yield parameters of chips, when using hot redundancy in SIMT processors is investigated. In the case of occurring defect on the chip, the hot redundant components are used for improving yield. Otherwise, they are used in order to improve the performance of chip. In this project, we examine systems,... 

Mixed-criticality embedded systems, as the next-generation of safety-critical systems, are increasingly employed in industry due to consolidating functionalities with varying criticality levels onto the same computing platform. Also, cost reduction and performance improvement encourage adoption of multicore platforms in these systems. Technology scaling, battery-supplied design and heavy computation in mixed-criticality systems necessitates employing energy management techniques. Due to the degrading effects of these techniques on the system’s reliability, reducing energy consumption without sacrificing the reliability requirement is a vital challenge in mixed-criticality systems, in... 

The advancement of Cyber-physical Systems (CPSs) has attracted attention to Mixed-Criticality Systems (MCSs), both in research and industrial designs. Mixed-criticality systems (MCSs) integrate different types of functionalities with varying levels of criticality onto the shared computing platform. The scheduling algorithms for MCSs must guarantee that all high criticality tasks are completed by their deadlines in different operation modes of the system. In addition to certification, as multi-core platforms are becoming a dominant trend in designing MCSs, simultaneous energy and reliability management, and Quality of Service (QoS) are other significant challenges in designing MCSs. Indeed,... 

Deep neural networks, as one of the main approaches in machine learning, play a crucial role in analyzing complex data and identifying hidden patterns. However, significant challenges such as high sensitivity to input errors, noise, and minor data variations still persist. One of the key strategies to address these challenges and improve the stability and accuracy of neural networks is the proper and optimal use of activation functions. Activation functions allow networks to process data non-linearly and extract more complex features from the data. However, an incorrect choice of activation function or suboptimal tuning can reduce the network's performance and make it more sensitive to input... 

Combining the concept of Network-on-Chip (NoC) with three dimensional integrated circuits technology on 3D NoC enables reduction of propagation delay, interconnect power consumption, and die area, as well as increase in system operational bandwidth. Nevertheless, reducing the feature size of semiconductor technologies has raised certain aging mechanisms, like Negative Bias Temperature Instability (NBTI) and Electromigration, as the main reasons for reduction in reliability and lifetime of NoCs. Reduction in die area results in an increase in power density of the chip, which exacerbates temperature-related concerns of 3D NoCs compared to 2D NoCs. Thus, the aging mechanisms that are directly... 

Combination of 3D stacking and network-on-chip (NoC), known as 3D NoC, has some advantages such as reduced propagation delay, chip area and interconnect, and power consumption, and bandwidth increase. Despite these advantages, the increased power density per chip area due to area decrease causes thermal problems in 3D NoCs to be more critical than 2D NoCs. Therefore, design of temperature management algorithms is essential for these systems. One of the dynamic thermal management techniques is task migration that balances generated thermal among cores.In this thesis, we propose a task migration scheme using feedback control for 3D NoCs. The main purpose of this scheme is to decrease the peak... 

Today, the use of data centers has drastically increased, and load balancing is one of the challenges of data centers. Generally, load balancing is the effective distribution of network traffic between service providers, and it has become more important due to the difference between the size of the network traffic and its unpredictable nature. Because of the difference between data center networks and wide area networks, special services have been provided to meet the needs of these networks. In this thesis, we intend to explain load balancing and characteristics of data centers, and then explore the particular methods of load balancing in data centers and divide them into two groups of... 

According to recent advancements in digital circuit technology and new constraints for digital systems, scholars have researched to find a replacement for traditional copper links that is used to connect the embedded processing elements in a chip. Optic NoCs and wireless NoCs are two promising solutions to overcome challenges in traditional NoCs.
In this thesis, an innovative 3D NoC architecture is proposed which consists of four 2D mesh-based networks and they are connected via four wireless sub-networks as backbones. It is estimated that, the proposed architecture shrinks the power consumption at least 35 percent relatively due to the gate-level simulations. Thus, a better scaling and... 

Most hardware manufacturers outsource the fabrication of their integrated circuits (ICs) to third party foundries in order to reduce the cost of silicon chip fabrication. This increases the vulnerability to malicious activities. Third party foundries may modify the circuit’s design or its physical parameters. These modifications are known as Hardware Trojan Horses (HTHs). An adversary can insert a Trojan in the design to disable and/or destroy a system, or leak information to the adversary. Several Methods are proposed for HTH Detection, and Design for Hardware Trust (DfHT) in the last decade. However, the lack of a comprehensive approach in this area is sensed. Moreover, the previously... 

The fast development of semiconductor industry has moved the design methodology to SoC (System on Chip) design. This growing trend has made it possible to perform parallel processing on a chip. Due to the increasing number of processing elements In SoCs, buses become the bottleneck of the system and lead to non-efficient designs. In the early years of the current decade, Network on Chip (NoC) was introduced and considered by the researchers. NoC is an efficient solution that eliminates bus bottleneck and it had been introduced as a suitable substructure for interconnecting processing elements. The NoCs were originally built based on Interconnection Networks. Although initially aimed at... 

The ever-expanding growth of internet traffic enforces deployment of massive Data Center Networks (DCNs) supporting high performance communications. Optical switching is being studied as a promising approach to fulfill the surging requirements of large scale data centers. Data center networks include hundreds of thousands of nodes that require flexible, high bandwidth, and low power infrastructures for their communications. Optical interconnection networks supply the required bandwidth, consuming much lower power compared to their electrical counterparts. The heterogeneous nature of data centers’ traffic needs a flexible network architecture which can be dynamically configured according to... 

Mixed-critical systems (MCSs) use a common hardware platform to schedule and execute tasks with multiple critical levels. Multi-core processors are commonly used by these systems, and batteries are frequently employed to provide the energy they require due to their portable nature or lack of access to large energy sources. Therefore, it is essential to use energy-management methods, such as dynamic voltage and frequency scaling (DVFS) and dynamic power management (DPM), to reduce their energy consumption. Using power/energy management methods can lead to missed deadlines due to increased execution time of tasks. In two-level mixed-critical systems, the lack of correct and timely execution of... 

An implementation of Digital Section of a DVB-T receiver has been introduced in this research. Nowadays, low-power and area-efficient designs have proven their importance in IC design aspect, so many low-power and area efficient approaches have been considered in this implementation. This design has been segregated into independent blocks, and each of them has been designed respect to the design goals. After that, all these blocks linked together and a whole system design implemented in gate level, then downloaded into a FPGA (Field programmable Gate Array) to test the timing and functionality of implemented blocks. In this thesis, some innovations have been introduced. A new algorithm for... 

Increasing complexity of modern embedded systems has caused tasks with different criticality levels to run on a shared hardware platform, called mixed-criticality systems. In these systems, it is important to use fault tolerant techniques to achieve reliability targets. Moreover, the limited battery life in many applications and real-time requirements make energy-aware reliability management and guaranteeing deadline constraints a major challenge. Checkpointing with rollback recovery is a good option to ensure reliability of these sys- terns because of its low cost and relatively low time overhead. However, improper use of this technique can impose high energy overhead and cause deadline... 

According to Moor’s law, the number of transistors per chip would double every 1.5 years. It means that the number of processors, memory and hardware cores available on the chip also increases. In SoC, a number of IP cores and communication links or buses are integrated on a chip. According to inefficiency of the interconnection bus used in SoCs for a large number of processors, NoC has been introduced in the beginning of the current decade. In the NoC paradigm a router-based network is used for packet switched on-chip communication among cores. A typical NoC architecture will provide a scalable communication infrastructure for interconnecting cores. One of the most important features of... 

Today convolutional neural networks (CNN) are very popular due to their high accuracy and robustness. As the size and complexity of CNNs grow, the demand for larger on-chip memories also increases. Given that off-chip access memory has a high cost, one solution is to enlarge on-chip caches by employing emerging multi-level Cell (MLC) STT-RAMs. This memory provides higher capacity at the cost of lower reliability. The root cause of low reliability of MLC STT-RAM is failure of read and write operations. However, MLC STT-RAM and CNNs are perfect matches in the sense that in one hand MLC STT-RAM provides higher capacity, on the other hand CNN can tolerates moderate level of inaccuracy and low... 

The development of deep neural networks is making tremendous progress in various fields, including processing Image, speech processing and other areas. Despite this tremendous achivement, neural networks have a lot of computational overhead and memory access that prevent them from being used in resource-constrained devices. We also know that many neural network applications are of great importance in mobile devices, and it is desirable for us to use their power in this regard. Many efforts have been done at different levels to solve the problem of executing deep neural networks on these devices. In this research, an approach based on offloading is used in which two different small (on the... 

Branch Target Buffer is a widely used component in modern processors. While there are different designs for BTB, they generally have a set-associative structure keeping branches and their target to help the frontend fetch the instructions on the correct path. To achieve high performance, it’s essential to obtain a high hit rate out of the BTB. Prior works has shown that BTB suffers from frequent misses that require large sizes or sophisticated BTB prefilling mechanisms to overcome the problem. However, the first solution imposes a significant storage overhead, and the latter results in limited benefits. Prior works have shown that branches exhibit different behaviors from being strongly...