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1, 3- Dipolar Cycloaddition Reactions of Azomethine Ylides of Ninhydrin with Chalcones and Investigation of Asymmetric Addition of TMSCN to Imines
,
M.Sc. Thesis
Sharif University of Technology
;
Saidi, Mohammad Reza
(Supervisor)
;
Jadidi, Khosrow
(Supervisor)
;
Mehrdad, Morteza
(Co-Advisor)
Abstract
Part 1
1,3-dipolar cycloaddition reactions offer convenient routes for the construction of a variety of five-membered heterocycles. This thesis represents a simple synthetic method via 1,3-dipolar cycloaddition reaction to prepare a novel class of spiro pyrrolidines and spiro pyrrolizidines which exhibit many biological activities. Non-stabilized azomethine ylides which generated in situ by the decarboxylative condensation of ninhydrin with proline and sarcosine were used as a 1,3-dipoles. On the other hand, chalcone and its derivatives with an impressive array of pharmacological activities were the dipolarophiles in these reactions. The reactions were carried out through reflax...
1,3-dipolar cycloaddition reactions offer convenient routes for the construction of a variety of five-membered heterocycles. This thesis represents a simple synthetic method via 1,3-dipolar cycloaddition reaction to prepare a novel class of spiro pyrrolidines and spiro pyrrolizidines which exhibit many biological activities. Non-stabilized azomethine ylides which generated in situ by the decarboxylative condensation of ninhydrin with proline and sarcosine were used as a 1,3-dipoles. On the other hand, chalcone and its derivatives with an impressive array of pharmacological activities were the dipolarophiles in these reactions. The reactions were carried out through reflax...
High-endurance and performance-efficient design of hybrid cache architectures through adaptive line replacement
, Article Proceedings of the International Symposium on Low Power Electronics and Design, 1 August 2011 through 3 August 2011 ; August , 2011 , Pages 79-84 ; 15334678 (ISSN) ; 9781612846590 (ISBN) ; Arjomand, M ; SarbaziAzad, H ; Sharif University of Technology
2011
Abstract
In this paper, we propose a run-time strategy for managing writes onto last level cache in chip multiprocessors where STT-RAM memory is used as baseline technology. To this end, we assume that each cache set is decomposed into limited SRAM lines and large number of STT-RAM lines. SRAM lines are target of frequently-written data and rarely-written or read-only ones are pushed into STT-RAM. As a novel contribution, a low-overhead, fully-hardware technique is utilized to detect write-intensive data blocks of working set and place them into SRAM lines while the remaining data blocks are candidates to be remapped onto STT-RAM blocks during system operation. Therefore, the achieved cache...
Application of Non-Volatile Memory Technogoies in Memory Hierarchy of CMPs
, M.Sc. Thesis Sharif University of Technology ; Sarbazi Azad, Hamid (Supervisor)
Abstract
In this paper, we propose a run-time strategy for managing writes onto last level cache in chip multiprocessors where STT-RAM memory is used as baseline technology. To this end, we assume that each cache set is decomposed into limited SRAM lines and large number of STT-RAM lines. SRAM lines are target of frequently-written data and rarely-written or read-only ones are pushed into STT-RAM. As a novel contribution, a low-overhead, fully-hardware technique is utilized to detect write-intensive data blocks of working set and place them into SRAM lines while the remaining data blocks are candidates to be remapped onto STT-RAM blocks during system operation. Therefore, the achieved cache...
Low power Clock and Data Recovery Circuits in 20Gb/s Range in CMOS Technology
, M.Sc. Thesis Sharif University of Technology ; Hajsadeghi, Khosrow (Supervisor)
Abstract
Growing demand for increased data transmission in communication systems and the internet, has intensified the need to increase the bandwidth of high speed transceivers. One of the main elements in high speed receivers is the clock and data recovery circuit which guarantees the transfer of data with high reliability. In this thesis, the design of a clock and data recovery circuit for high frequency applications is considered. The aim of this project is the design of a circuit with low power and low jitter for high-speed input data. A new four stage LC ring oscillator is designed that works at the quarter rate of the input. A new idea for the design of the binary phase detectors has also been...
Speckle Noise Reduction Using Adaptive Filters with Application to SAR Images
, M.Sc. Thesis Sharif University of Technology ; Hajsadeghi, Khosrow (Supervisor)
Abstract
SAR image noise is a significant problem for SAR image analysis.The inherent noise of SAR images, known as speckle, seriously affects the SAR image interpretation. It also has adverse effects on the classification and segmentation of SAR images. Due to its great significance, the SAR image processing has received considerable attention in recent years and many researchers have developed techniques to reduce the inherent noise accompanying the SAR images. A survey of the literature shows that the wavelet analysis is one of the most common methods used for speckle reduction. While the power of the morphological analysis method has mostly not been recognized, we have utilized this efficient...
Design of Clock and Data Recovery Circuits Inmulti Gb/s Range in CMOS Technology
, M.Sc. Thesis Sharif University of Technology ; HajSadeghi, Khosrow (Supervisor)
Abstract
Some applications need fast locking clock and data recovery circuits for example the circuits that operate in burst mode must lock to the data packets which are transmitting from different transmitters very quickly and in just a few bit times. In such applications open-loop clock and data recovery circuits are used because lock time in closed-loop clock and data recovery circuits is usually much longer.
In this thesis a new open loop clock and data recovery circuit based on injection locking method has been proposed. This circuit can be used in applications such as passive optical networks that need fast locking. In this architecture a super harmonic injection-locked frequency divider...
In this thesis a new open loop clock and data recovery circuit based on injection locking method has been proposed. This circuit can be used in applications such as passive optical networks that need fast locking. In this architecture a super harmonic injection-locked frequency divider...
A 12 Bit Delta-Sigma Modulator For Wireless Applications
, M.Sc. Thesis Sharif University of Technology ; Hajsadeghi, Khosrow (Supervisor)
Abstract
Analog to digital converters are one of the most important component of Bluetooth and GSM receivers. The pipeline and Successive Approximation Register (SAR) ADCs are mainly used in these receivers. However, the pipeline ADCs consume lots of power and SAR ADCs suffer the resolution in advanced technologies. On the other hand, the Delta-Sigma ADCs are capable of achieving high resolution with a low power. So in this thesis, the various kinds and different implementations of Delta-Sigma Modulators are introduced. The system level design and the conversion between Discrete-Time Modulators and Continuous-Time Modulators are explained. The non-ideality effects such as limited gain and bandwidth...
Density and Level Monitoring and Control in Polypropylene Plants
, M.Sc. Thesis Sharif University of Technology ; Hajsadeghi, Khosrow (Supervisor)
Abstract
Polypropylene plants receive propylene monomer and produce polypropylene polymer by inducing chemical reactions under high pressure and high temperature conditions. In these plants it is essential to monitor and carefully control the density and level of the material contents in slurry high pressure and high temperature reactors and vessels. Due to process conditions and the advantages of the non contact measuring method we use radioactive level and density measurement method specially gamma ray level and density detectors and transmitters in P.P plants. Sometimes, however known and unknown natural or manmade factors may affect the performance of these devices. The known factors such as NORM...
Time to Digital Converters for ADPLL Applications
, Ph.D. Dissertation Sharif University of Technology ; Hajsadeghi, Khosrow (Supervisor)
Abstract
Effect of resolution of Time to Digital Converters (TDCs) on the performance of All-Digital Phase Locked Loops (ADPLLs) and capability of achieving higher resolution in advanced technologies lead to introducing different kinds of TDCs. Beside the analysis of different kinds of TDCs, This thesis proposes three new TDCs based on the time amplifi-cation concept. A new pipeline TDC is designed using a wide dynamic range time amplifi-er. A new method is used to widen dynamic range of the conventional time amplifiers. In order to get a low power high resolution conversion, a new delay element design is devel-oped to reduce the delay value and its sensitivity to mismatch and process variations....
Non-End-to-End Sign Language Translation with Large Language Models
, M.Sc. Thesis Sharif University of Technology ; Hajsadeghi, Khosrow (Supervisor)
Abstract
In this thesis, we study the task of sign language translation using a non-end-to-end framework by utilizing large language models. The proposed method initially generates a sequence of glosses corresponding to a sign language video through a continuous sign language recognition model, which is then considered as input for a language model. The role of a language model in this framework is to translate the sequence of glosses into coherent sentences in spoken language. Given the limited training resources available for machine translation models on the specific problem of sign language to text translation, leveraging large language models can be highly beneficial due to the accumulated...
Evaluation of Implementing Machine Learning Methods on Multi-Access Edge Computing Based Networks, Focusing on Computation Offloading
, M.Sc. Thesis Sharif University of Technology ; Hajsadeghi, Khosrow (Supervisor)
Abstract
Many applications that require heavy processing, such as augmented reality, facial recognition, self-driving cars, and digital healthcare systems, are emerging. Many devices in the Internet of Things space cannot process such a volume of calculations. One of the newest methods to solve this problem is using new architectures in network design, among which we can refer to the edge computing architecture. In this method, by offloading the computation on the available computing resources close to the network's end nodes, we try to provide the results of the calculations for the end nodes of the network as quickly as possible. In this thesis, the problem of determining the computation offloading...
High-endurance and performance-efficient design of hybrid cache architectures through adaptive line replacement
, Article Proceedings of the International Symposium on Low Power Electronics and Design ; 2011 , p. 79-84 ; ISSN: 15334678 ; ISBN: 9781612846590 ; Arjomand, M ; Sarbazi-Azad, H ; Sharif University of Technology
2011
Abstract
In this paper, we propose a run-time strategy for managing writes onto last level cache in chip multiprocessors where STT-RAM memory is used as baseline technology. To this end, we assume that each cache set is decomposed into limited SRAM lines and large number of STT-RAM lines. SRAM lines are target of frequently-written data and rarely-written or read-only ones are pushed into STT-RAM. As a novel contribution, a low-overhead, fully-hardware technique is utilized to detect write-intensive data blocks of working set and place them into SRAM lines while the remaining data blocks are candidates to be remapped onto STT-RAM blocks during system operation. Therefore, the achieved cache...
The Application of Ultrasonic Waves for Determining the Liquid Level in Reactor for Monitoring a Process Reactor
, M.Sc. Thesis Sharif University of Technology ; Hajsadeghi, Khosrow (Supervisor)
Abstract
In this research non-contact ultrasonic based method is used for liquid level measurement in a container. A system has been designed and developed to determine the liquid level and show the results on a personal computer. The system contains three main parts, which are mechanical and electronic parts and the programming. The setup can measure the liquid level with the accuracy of 1cm. An ATMEGA8 microprocessor commands to relays and controls the pumps. The pumps are used to change the height of the liquid in the containers to accurately calibrate the sensor and test its operation. The ultrasonic sensor, which is mounted above the vessel, transfers the data to an ATMEGA64 microprocessor for...
Direction of Arrival Estimation and Digital Beamforming in the Presence of Mutual Coupling Effects and Implementation
, Ph.D. Dissertation Sharif University of Technology ; Haj Sadeghi, Khosrow (Supervisor)
Abstract
Different beamforming methods are prevalent in wireless and mobile communication systems. However, a lot of practical issues, such as the quality of these methods in compact arrays and the huge computational burden are the major defects of the proposed methods. These problems restrict most of the algorithms to the theoretical domain and render them anappropriate for commercial applications. Therefore, the major focus of this thesis is on the practical issues in the implementation of the digital beam steering and direction of arrival estimation systems for linear, circular and random array configurations. To do so, compact arrays with super directivity are presented and considered. Different...
Security and Configuration Improvement in TETRA Systems
, M.Sc. Thesis Sharif University of Technology ; Haj Sadeghi, Khosrow (Supervisor)
Abstract
TETRA (TErrestrial Trunked RAdio) is one of the mobile telecommunication standards which has improved in several aspects (voice, data, video, coverage, etc.), especially the security section during the last two decades. Although communication could be quite secure in TETRA when the encryption is used, however, attackers create new ways to bypass the encryption without the knowledge of the legitimate user. Security is performed in different levels and forms to create reliable operation and to protect information through the transmission path from interception and tampering. Since most of the TETRA users require the highest possible level of security, in this thesis we introduce a new...
Design of Radio Frequency CMOS Power Amplifier for Cellular Telephony
, M.Sc. Thesis Sharif University of Technology ; Haj Sadeghi, Khosrow (Supervisor)
Abstract
A Radio Frequency Power Amplifier was designed for IS-95 standard in 0.18μm / 1.8V CMOS technology. In order to increase output voltage swing and protect gate oxide of devices, pseudo-differential cascode topology was exploited. Bondwire inductors with exact modeling were used to tune out parasitic capacitances. A low-pass, L match impedance transformation network, realized using bondwire inductors, was used at output of power amplifier. An impedance transformation network design process was developed which considers the quality factor of inductors, from the first step. Also having examined the nonlinearity phenomena in power amplifiers, a fast simulation or measurement method was proposed...
EEG Signal Processing in BCI Applications
, M.Sc. Thesis Sharif University of Technology ; Haj Sadeghi, Khosrow (Supervisor)
Abstract
Brain-inspired methods are now widely used to process the data generated by the brain with the aim of improving our understanding of how the brain functions and produces the remarkable intelligence exhibited by humans, which is the source of all realizations, perception and actions. Therefore brain-computer interface (BCI) is one of the most challenging scientific problems which focuses scientists attention, in most cases these systems are based on EEG signals recorded from the surface of the scalp because this method of the brain activity monitoring is noninvasive, easy to use and quit inexpensive. Brain computer interface (BCI) systems analyse the EEG signals and translate person’s...
Intelligent Diagnosis of Cardiovascular Disease using ECG Signals
, M.Sc. Thesis Sharif University of Technology ; Haj Sadeghi, Khosrow (Supervisor)
Abstract
Cardiovascular diseases (CVDs) have ranked first cause of deaths globally. In 2016, about 17.7 million people died from CVDs representing 31% of all world deaths. So, early intelligent detection of cardiovascular disease could help to save many lives in worldwide. There are several methods to analyze heart activity and to detect any abnormalities including Electrocardiogram, Stress test, Echocardiography, cardiac catheterization and coronary angiography.Among all methods, Electrocardiogram (ECG) is the most common and convenient type where it measures heart electrical activity and records it as a series of pulses. Analyzing these pulses would provide useful information about normal and...
SRAM Cell Design for Low Power Applications
, M.Sc. Thesis Sharif University of Technology ; Haj Sadeghi, Khosrow (Supervisor)
Abstract
From the cache of the personal computers to the main memory unit of SOCs, medical and wearable chips, Static Random Access Memory (SRAM) is widely utilizes. Preferable performance for SRAM varies with regard to the operating field. For instance, high speed access and performance is emphasized in the design of the cache for PCs. In contrast, power consumption and the area of the memory are the key design considerations for SOCs. Hence, the field in which SRAM is used, should be thoroughly studied. SOCs and medical chips suffer limitations in design due to using batteries as the source of energy and SRAMs consume a significant part of total power and occupy a large area on these chips. One of...
Vision Based Human Action Recognition using Deep Learning
, Ph.D. Dissertation Sharif University of Technology ; Haj Sadeghi, Khosrow (Supervisor)
Abstract
Temporal action localization in untrimmed videos is one of the significant challenges in computer vision, as accurately identifying the temporal boundaries of actions and classifying them remains difficult, with no optimal solution proposed thus far. In this thesis, two innovative methods are introduced to address this challenge and enhance the performance of temporal action localization (TAL). The first method involves designing an end-to-end neural network that utilizes error estimation to achieve precise action localization. The proposed method enhances temporal localization and action classification by simultaneously optimizing the network structures. To improve the accuracy of temporal...