Sharif Digital Repository

A 1.8V, 10-Bit, 40-MS/s Pipeline analog-to-digital converter designed using 0.18-μmCMOS technology is presented. The new structure of the A/D converter is based on double sampling and averaging techniques. By the first technique, all the stage amplifiers are active at the both sampling and holding cycles. Averaging as the second technique minimizes the capacitance mismatch and exchanges the priority of input-referred noise and capacitance mismatch in the selection of the stage caps. The converter achieved a peak spurious-free- dynamic-range of 61 dB, maximum differential nonlinearity 0.5 of least significant bit (LSB), maximum integral linearity of 0.9 LSB, and power consumption of 5mW.... 

The design of a complex active-RC filter for low-IF Wireless applications is described. Fifth-order complex Butterworth filter is designed using Class-AB operational amplifier architecture. This new structure makes the filter suitable for low power applications with high dynamic range. Simulation results show that the filter provides more than 40 dB image rejection ratio (IIR) and dynamic range of 82dB. The complete filter including on-chip tuning circuit consumes only 4.3mW with 1.8V single supply voltage. © 2007 IEEE  

In this paper, a fourth-order, 3.5-MHz, low-pass elliptic Gm-C filter employing low-noise, low-voltage transconductance amplifiers is presented. A new technique to enhance the linearity of the Gm-C filter is proposed. Furthermore, the nonlinear behavior of the filter caused by nonlinear behavior of transconductors with determined input amplitude is discussed. HSpice simulation results of the 1.8-V filter in a 0.18μm CMOS process show a THD of less than 44dB for 0.6Vpp input signal and an input-referred noise of less than 45 nV/√Hz in worst case. The current consumption of each OTA is 1.5-mA. © 2006 IEEE  

A new single-bit cascaded 2-2 σ/δ (Sigma-Delta) modulator with only two op-amps, instead of four ones in conventional modulators, to decrease the static power consumption and area, is designed for GSM transceiver applications. The circuit consists of two new single op-amp, second-order, and low-pass loop filters to achieve a fourth-order quantization noise shaping. The modulator shows 84dB DR (Dynamic Range) for GSM signal bandwidth, while consuming 2.3mW from a 2.5V supply voltage. © 2003 IEEE  

In this paper we propose a novel structure of a discrete-time mixed-signal linear equalizer designed for analog front end of Gigabit Ethernet receivers. The circuit is an FIR filter which involves 6 taps based on a coefficient-rotating structure. Here, a simple structure is used for merging digital to analog conversion of the filter's coefficients and multipliers needed for 6 taps. This structure results in high speed and low power dissipation as well as less A/D converter complexity. Simulated in a 0.18 um CMOS technology, this equalizer operates at 125 MHz while dissipating 10 mw from a 1.8 V power supply. © 2006 IEEE  

A new second order sigma delta modulator with the reduced number of op-amps, to decrease static power consumption and area, is presented for voice band applications such as codecs. This switched capacitor modulator uses reused capacitor technique to reduce the input thermal noise and circuit area. It improves the DR of modulator by almost 0.5 bit. The modulator shows 87 dB DR for voice band while consuming 125 μW from a 2.5 V supply. © 2003 IEEE  

A 3rd order, 1.1 MHz, lowpass butterworth Gm-c filter has been combined with a low noise Variable Gain Amplifier to form the Variable Gain Filter (VGF). In this VGF an improved transconductor is used and a new method is used to adjust the transconductance gain for tuning application. A continuous variable gain current-to-current converter is used to tune the transconductor value. The THD of the VGF is -85 dB for 1 Vppd input signal and -50 dB for 3 Vppd input signal. VGF gain can be varied from 0 to 31 dB with 1 dB variation steps. Input referred noise is 20 nV/√Hz for maximum gain. All the circuits are designed based on a 0.25 μm CMOS process technology  

In this paper a new low-voltage two-stage class-AB line driver for ADSL applications is presented. The new proposed line-driver consists of only two stages with a new method to control the quiescent current of the output stage. The low-voltage full-CMOS high-linear line driver shows -77 dB THD for a load as low as 20 ohms. The line driver has variable gain, attenuating the input signal from 0dB to -14dB with 2dB steps. The peak to peak differential output swing is 4.2-V from a 2.5-V Supply voltage in a 0.25um standard CMOS technology  

A 4th order, 5 MHz, lowpass Butterworth Gm-c filter has been combined with a low noise low-voltage amplifier to form a lowpass filter for video applications. In this filter an improved transconductor and a powerful method is used to adjust the transconductance gain for tuning application. A continuous variable gain current-to-current converter is used to tune the transconductor value. The THD of the filter is -77 dB for 1 Vppd input signal. Input referred noise is 40 nV/√Hz in the worst case. All the circuits are designed based on a 0.25 μm CMOS process technology with a single 1.8 V supply. © 2002 IEEE  

A new, ultra low-voltage, linear CMOS OTA will be described. A 4th order, 18 MHz low pass Butterworth Gm-C filter has been designed with this new OTA stage for video applications. In this filter a new, fully digital approach has been used for frequency tuning. The THD of the filter for input signal 0.5 VPPis better than -60 dB. All of circuits are designed based on 0.25 um CMOS process technology with a single 1-volt power supply  

A low voltage high speed class AB op-amp with new structure is presented. The proposed op-amp has been designed to drive a large capacitive load as large as 10 pf dedicated for high-resolution high-speed pipelined analog to digital converters. Consuming comparatively low power about 6 mw, the proposed class AB op-amps has an output swing of 2.6 Vpp from a single supply of 1.5 volt. It has been observed that this op-amp can be suitable for a 1.5 volt 13-bit Pipelined A/D with sampling rate of 60 MS/S. This op-amp is to be fabricated in standard 0.18u CMOS technology  

A low voltage bandgap reference (BGR) in CMOS technology, with high power supply rejection ratio (PSRR) is presented. The proposed circuit uses a regulated current mode structure and some feedback loops to reach a low voltage, low power and high PSRR voltage reference. The circuit was designed and simulated in 0.25um CMOS technology, with a power supply of 1 volt. The results show PSRR is below -70dB at 1MHz and the output voltage variation versus temperature (0-70) is less than 0.3%. This circuit shows robustness against process variation  

Learning a foreign language encompasses a process of trial and error that can lead to the progression of the learner's interlanguage, meaning that the learners make use of their language knowledge that receives feedback and brings about progress through diagnosis of the problems and being corrected by the teacher. Therefore, there exists a need to analyze the underlying reasons causing the students to remain taciturn with a low willingness to communicate (WTC) during a language class. There has been much work done investigating the role of the learner's stable personal characteristics (traits) along with their situational changes at a specific time (states) that influence the student's... 

Using 3-D scanned data to analyze and extract pore network plays a vital role in investigation of porous media's characteristics. In this paper, a new simple method is developed to detect pores and throats for analyzing the connectivity and permeability of the network. This automated method utilizes some of the common and well-known image processing functions which are widely accessible by researchers and this has led to an easy algorithm implementation. In this method, after polishing and quality control of images, using city-block distance function and watershed segmentation algorithm, pores and throats are detected and 3-D network is produced. This method can also be applied on 2-D images... 

In this paper, we try to recognize and distinguish different groups of arrhythmia using novel features which have been obtained from the heart rate's phase space in recent years. For this purpose, we used Triangular Phase Space Mapping (TPSM) and Parabolic Phase Space Mapping (PPSM). For recognition, we used three groups of 15 subjects using the Physionet database (Arrhythmia, Congestive Heart Failure (CHF), and Atrial Fibrillation (AF)) with Normal Sinus Rhythm (NSR). The obtained features discriminate arrhythmia from NSR by p