Sharif Digital Repository

This paper proposes a low-cost fault-tolerant Carry Look-Ahead (CLA) adder which consumes much less power and area overheads in comparison with other fault-tolerant CLA adders. Analytical and experimental results show that this adder corrects all single-bit and multiple-bit transient faults. The Power-Delay Product (PDP) and area overheads of this technique are decreased at least 82% and 71%, respectively, as compared to adders which use traditional TMR, parity prediction, and duplication techniques. © 2009 IEEE  

This paper introduces Adaptive Path Selection and Loading (APSL) as a multi-path data transmission scheme for mitigating the effects of misbehaving nodes in mobile ad-hoc networks. In APSL, misbehavior resilience is achieved by adaptively loading Reed-Solomon (RS) coded data into multiple node-disjoint paths. In order to maximize packet delivery ratio, paths are loaded according to Path State Information (PSI) which dynamically estimates the availability and stability of each path. We evaluated APSL through simulation in terms of packet delivery ratio, normalized average end-to-end delay and overhead. APSL can achieve more than 90% packet delivery ratio. Compared to adaptive single path and... 

A wireless sensor network with a large number of small sensor nodes can be used as an effective tool for gathering data in various situations. Energy is a critical resource in wireless sensor networks and system lifetime needs to be prolonged through the use of energy-aware strategies during system operation. Routing protocols in WSNs might differ depending on the application and network architecture. Many routing protocols have been specifically designed for WSNs where energy awareness is an essential design issue. The aim of this paper is to evaluate the efficiency of a routing protocol named directed flooding which is a fault-tolerant and energy efficient routing protocol for wireless... 

This paper analyzes the problem of transient-error recovery of several protecting techniques used in fault-tolerant cache memories. In this paper, reliability and mean-time-to-failure (MTTF) equations for several protecting techniques are derived and estimated. The results of the considered techniques are compared with those of cache memories without redundancies and with only parity codes in both tag and data arrays of caches. Depending on the error rate under which a cache memory will operate, and the size of the cache memory, one of the analyzed cases could be used. If the transient-error rate is very small or the size of cache memory is relatively small, then a protected with only single... 

The advancement in technology, information and communication has forced banks and financial institutions into hard competition. In this new era technology, people and customer are the elements which the banks are concentrating on them to manage customer relationship and success of banking in customer satisfaction. Electronic customer relationship management (e-CRM) is seen to arise from the consolidation of traditional CRM with the e-business applications marketplace and has created a flurry of activity among companies. The purpose of this study is to examine the competitive advantages on e-CRM in financial institutions and banks and obtain better understanding of the e-CRM benefits. A... 

The switch level is an abstraction level between the gate level and the electrical level, offers many advantages. Switch level simulators can reliably model many important phenomena in CMOS circuits, such as bi-directional signal propagation, charge sharing and variations in driving strength. However, the fault simulation of switch level models is more time-consuming than gate level models. This paper presents a method for fast fault emulation of switch level circuits using FPGA chips. In this method, gates model switch level circuits and we can emulate mixed gate-switch level models. By the use of this method, FPGA chips can be used to accelerate the fault injection campaigns into switch... 

This paper presents a behavior-based error detection technique called Control Flow Checking using Branch Trace Exceptions for PowerPC processors family (CFCBTE). This technique is based on the branch trace exception feature available in the PowerPC processors family for debugging purposes. This technique traces the target addresses of program branches at run-time and compares them with reference target addresses to detect possible violations caused by transient faults. The reference target addresses are derived by a preprocessor from the source program. To enhance the error detection coverage, three other mechanisms, i.e., Machine Check Exception, System Trap Instructions and Work Load Timer... 

This paper presents a circuit level soft error-tolerant-technique, called RRC (Robust Register Caching), for the register file of embedded processors. The basic idea behind the RRC is to effectively cache the most vulnerable registers in a small highly robust register cache built by circuit level SEU and SET protected memory cells. To decide which cache entry should be replaced, the average number of read operations during a register ACE time is used as a criterion to judge. In fact, the victim cache entry is one which has the maximum read count. To minimize the power overhead of the RRC, the clock gating technique is efficiently exploited for the main register file resulting in... 

By technology down scaling in nowadays digital circuits, their sensitivity to radiation effects increases, making the occurrence of soft errors more probable. As a consequence, soft error rate estimation of complex circuits such as processors is becoming an important issue in safety- and mission-critical applications. Fault injection is a well-known and widely used approach for soft error rate estimation. Development of previous FPGA-based fault injection techniques is very time consuming mainly because they do not adequately exploit supplementary FPGA tools. This paper proposes an easy-to-develop and flexible FPGA-based fault injection technique. This technique utilizes debugging facilities... 

This paper presents a low cost fault-tolerant technique so called OWHR (Operand Width Aware Hardware Reuse) to ALU design in embedded processors. The OWHR technique is motivated by two facts: (1) Many of the produced and consumed values are narrow-width values in the embedded processors, i.e. they have leading zeros or ones in their most significant bits. This indicates that only a fraction of the circuit is performing useful operations when a particular arithmetic or logic circuit in the ALU is operating on narrow-width values; (2) other circuits of the ALU are not used, when a particular arithmetic or logic circuit is being utilized to perform a specific operation in the ALU in the... 

The continuous decrease in CMOS technology feature size increases the susceptibility of such circuits to single event upsets (SEU) caused by the impact of particle strikes on system flip flops. This paper presents a novel SEU-tolerant latch where redundant feedback lines are used to mask the effects of SEUs. The power dissipation, area, reliability, and propagation delay of the presented SEU-tolerant latch are analyzed by SPICE simulations. The results show that this latch consumes about 50% less power and occupies 42% less area than a TMR-latch. However, the reliability and the propagation delay of the proposed latch are still the same as the TMR-latch. the reliability of the proposed latch... 

This paper proposes a Numeral-Based Crosstalk Avoidance Coding (NB-CAC) to protect communication channels of Network-on-Chips (NoCs) against crosstalk faults. The NB-CAC scheme produces codewords without bit patterns '101' and '010' to eliminate harmful transition patterns from NoC channels. This is done by the use of a new numeral system proposed in the paper. Using the proposed numeral system, the NB-CAC scheme 1) can be utilized in NoC channels with any arbitrary width, and 2) can be implemented with low area, power, and timing overheads. VHDL and SPICE simulations have been carried out for a wide range of channel widths to evaluate delay, area, and power consumption of the NB-CAC codecs.... 

This paper presents a cost-efficient technique to jointly use circuit- and architecture-level techniques to protect an embedded processor's register file against soft errors. The basic idea behind the proposed technique is robust register caching (RRC), which creates a cache of the most vulnerable registers within the register file in a small and highly robust cache memory built from circuit-level single-event-upset-protected memory cells. To guarantee that the most vulnerable registers are always stored in the robust register cache, the average number of read operations during a register's lifetime is used as a metric to guide the cache replacement policy. A register is vulnerable to soft... 

This paper presents a fault tolerant and energy efficient write-back set-associative cache, which has a heterogeneous structure. The cache architecture is based on partitioning the ways of each set into two different parts. In each set, one cache way uses SECDED code and maintains dirty blocks while the other ways employ parity bit and keep clean blocks. To evaluate the set-associative cache, SIMPLESCALAR tool and CACTI analytical model are used. The experimental results show that as the feature size decreases and the associativity increases, the energy saving of the proposed cache increases. The experimental results express that for an 8-way setassociative cache in 32nm, about 7% area and... 

The ODYSSEY design methodology has been recently introduced as a viable solution to the increasing design complexity problem in the ASICs. It is an object-oriented design methodology which models a system in terms of its constituting objects and their corresponding method calls. Some of these methods are implemented in hardware; others are simply executed by a general purpose processor. One fundamental element of this methodology is a network on chip that implements method invocation for hardware-based method calls. However this network is prone to faults, thus errors on it may result into system failure. In this paper an architectural fault-tolerance enhancement to the ODYSSEY design... 

Soft-errors are increasingly considered as a major cause for computer system failures. Software techniques are used as cost-effective and flexible techniques to tolerate soft-errors but the introduced overhead is not acceptable in some safety-critical real-time systems. The identification of the program blocks and protecting only vulnerable blocks against soft-errors reduces the performance overhead. In this paper, we present a genetic algorithm to identify the vulnerable program blocks as well as the derating program blocks against soft-errors. Then, only vulnerable blocks are protected by some software-based soft-error tolerance techniques to achieve a lower performance and space overhead.... 

In this paper, we have proposed a fast and easy-to-develop FPGA-based fault injection technique. This technique uses the Altera FPGAs debugging facilities in order to inject SEU fault model in both flip-flops and memory units. Since this method uses the FPGAs built-in facilities, it imposes a negligible performance and area overhead on the system. The experimental results on Leon2 processor shows that the proposed technique is on average four orders of magnitude faster than a simulation-based fault injection  

Spin-transfer-torque RAMs (STT-RAMs) are the most promising technology for replacing Static RAMs (SRAMs) in on-chip caches. One of the major problems in STT-RAMs is the high error rate due to stochastic switching in write operations. Cache replacement algorithms have a major role in the number of write operations into the caches. Due to this fact, it is necessary to redesign cache replacement algorithms to consider the new challenges of STT-RAM caches. This paper proposes a cache replacement algorithm, which is called least error rate (LER) , to reduce the error rate in L2 caches. The main idea is to place the incoming block in a line that incurs the minimum error rate in write operation.... 

SRAM-based scratchpad memories (SPMs) used in embedded systems impose high leakage power. Designing SPMs based on non-volatile memories (NVMs) were proposed as NVMs have negligible leakage power. The main problem of utilizing NVMs across the SPM is their limited number of write cycles (endurance). This problem threatens the reliability of NVM-based SPMs. To alleviate the problem of limited endurance in NVM-based SPMs, this paper proposes a method, called overwrite purging through in-execution memory address snooping (OPTIMAS). The main idea behind the proposed method is to control the lifetime of NVM-based SPMs, directly by a hardware unit, outside of the SPM mapping algorithm. This idea... 

This paper presents a behavior-based error detection technique called Control Flow Checking using Branch Trace Exceptions for PowerPC processors family (CFCBTE). This technique is based on the branch trace exception feature available in the PowerPC processors family for debugging purposes. This technique traces the target addresses of program branches at run-time and compares them with reference target addresses to detect possible violations caused by transient faults. The reference target addresses are derived by a preprocessor from the source program. The proposed technique is experimentally evaluated on a 32-bit PowerPC microcontroller using software implemented fault injection (SWIFI)....