Sharif Digital Repository

Ever increasing applications of embedded systems have motivated the designers to pay special attention to the design requirements of such systems. Among embedded applications, safety-critical systems have high reliability requirements as failures in such systems may endanger human life or result in catastrophic consequences. Embedded processors as the computation cores of embedded systems are very crucial from reliability point of view. This is because; a failure in the processor most probably leads to a system failure. One effective way to protect embedded processors against environmental faults is to use system level fault-tolerant techniques such as Master/Checker (M/C) or Triple Modular... 

In recent years, the use of embedded processors has grown increasingly in wide range of computer systems; so that most of manufactured CPUs are used in emebedded systems many of which are safty-critical systems such as medical devices, aircraft flight control, space systems, nuclear systems, etc. The incidence of failure in these systems can cause irreversible damages on human life, financial or environmental matters. Silicon process technology trends, such as reducing the threshold voltage, increasing the frequency and decreasing the size of transistors, not only caused increase in single-bit fault rate but also caused occurance of multi-bit faults. Due to importance ofcorrect operation of... 

Nowadays, one of the most important challenges in the design of digital circuits is their susceptibility to the strike of high energy particles which leads to the Single Event Transient (SET) and Multiple Event Transients (MET). In fact, technology scaling which results in lower supply voltage, higher operating frequency, and lower nodal capacitance, makes today’s digital circuits more susceptible not only to high energy particles but also to low energy particles. Moreover emerging deep sub-micron technologies and the integration of more cells in today’s chips have caused higher probability of MET occurrences. A lot of research has tried to reduce the soft error rate due to high energy... 

Wireless Sensor Networks (WSNs) are prone to faults due to battery depletion of nodes, where a node failure can disturb routing, as it plays a key role in transferring sensed data to the end users. A WSN may be partitioned into groups of nodes called clusters; for every cluster, there is a node, called Cluster Head (CH) that is responsible for collecting and transferring data from all nodes in that cluster. This means that the CH is a single point of failure; i.e., once a CH fails, the whole cluster will fail, which leads to inability of its members for transferring data outside the cluster. This thesis presents a Fault-Tolerant and Energy-Aware algorithm (FTEA), which prolongs the lifetime... 

Vulnerability of SRAM-based FPGAs to soft errors signals the importance of applying fault-tolerant methods in FPGAs used in safety-critical applications. Previous methods to protect SRAM-based FPGAs impose significant area and power overheads. Additionally, they suffer from susceptibility of configuration bits to Single Event-Multiple Upsets (SEMU). This thesis presents a Highly Available Fault-Tolerant Architecture (HAFTA) to protect SRAM-based FPGA designs against SEMUs in both configuration and user bits. In HAFTA, the entire design is duplicated and the main and replica flip-flops are compared at each clock cycle to detect any possible mismatch. To save the latest correct state of the... 

The increasing size of valuable data emphasizes the importance of applying reliability in storage systems. One way to protect storage system failures is using erasure codes. The advantages of using erasure codes are their low overheads and high reliability. Soft errors caused by high-energetic particles do not only corrupt data in the SSD-based storage systems, but also in the erasure codes. In this regards, it is important to protect erasure code implementations against soft errors. This thesis proposes a fault-tolerant implementation of erasure codes. The proposed method is based on the structure of each erasure code. This method is analytically evaluated on four erasure codes, i.e.... 

With continuous device down-scaling and increase in transistor counts on a chip, complementary metal-oxide-semiconductor (CMOS) technology has become extremely sensitive to soft errors. Soft errors are transient errors caused by energetic particles such as neutrons and alpha particles. An essential step to design a soft error tolerant digital system with minimal performance and power overheads is Soft Error Rate (SER) estimation of system components. Until recently, Single Event Upsets (SEUs) in latches and Filp-Flops (FFs) and Single Event Transients (SETs) in combinational logic parts of digital circuits were regarded as the main effects of particle strikes. However, with the emerging... 

Increasing complexity of embedded systems and the need for more computation powerhave directed designers toward using of multiprocessors. SRAM-based FPGAs are suitable platforms for implementation of multiprocessors due to thier low cost, fast time-to-market and re-configurability. FPGA-based multiprocessors are known as soft multiprocessors. The large area of SRAM-based FPGAs is occupied by configuration bits. Configuration bits are vulnerable to high energy particles that can lead to soft errors. In this regards, it is of decisive importance to protect soft multiprocessors against soft errors. This thesis proposes a fault-tolerant method for soft multiprocessors that can detect and... 

The use of flash-based Solid State Disks (SSDs) has been increased in the past decades because of their high performance and low power consumption. As SSDs have no moving mechanical parts, they are more reliable than HDDs. SSDs have specific errors, such as read, program, and erase disturbs, data retention, and endurance. It is so common in storage systems to apply an array of disks called Redundant Array of Independent Disks (RAID) together for the aim of reliability and performance. Erasure codes are one of the main methods applied in storage systems for the aim of reliability. Erasure codes increase the reliability of storage systems by protecting them against disk failures and sector... 

One of the major challenges that threat the reliability of NoC-based systems is Crosstalk fault. Some effects of crosstalk fault such as Rising/falling delays and rising/falling speed-ups lead to the variations in channel delay, incorrect data transmission, and extra power consumption in NoC communication channels. Crosstalk fault is data dependent and the intensity of this fault seriously depends on the transition patterns appearing on the wire during the data traversal between processing elements. Most of mechanisms tackling crosstalk fault that are discussed in literature are based on 3-wire delay model. In 3-wire delay model, one wire is considered as victim wire and classification of... 

Wireless Sensor Networks (WSNs) consist of sensor nodes that are connected to each other and are widely used in many applications to acquire and process information. WSN nodes are battery powered, therefore energy management is a key factor for long live network. Node radio transceiver unit uses the most part of energy resource of the node and as a result limits the network lifetime. One way to prolong lifetime of network is to utilize routing protocols to manage energy consumption. To have an energy efficient protocol, we can apply cluster organization on the network, where sensor nodes are partitioned into groups called cluster. Then, the whole cluster data is sent through Cluster Head... 

Three-dimensional network-on-chip (3D NoC), the combination of NoC and die-stacking 3D IC technology, is motivated to achieve lower latency, lower power consumption, and higher network bandwidth. 3D NoCs reduce length of communication link and transmition delay by die stacking. However, the length of heat conduction path and power density per unit area increase as more dies are stacked vertically. High temperature results in longer propagation delay and increases the leakage power. If heat production in the chip is not managed, low cooling rate for these layers is a threat for the chip performance and reliability. To solve the thermal problems, thermal management schemes were proposed in the... 

On-chip caches are regarded as a solution for increasing performance gap between main memory and CPU. In recent years, with the development in the performance of processing cores, the demands for larger on-chip caches are also increased. With the technology scaling trend, SRAM-based on-chip caches suffer from limited scalability, high leakage power consumption and vulnerability to soft errors. Among emerging non-volatile memories, STT-MRAMs are the most promising alternative for SRAMs in large last-level on-chip caches due to their higher density and near zero leakage power. However, the reliability of STT-MRAMs is threatened by soft and hard errors. Soft errors in STT-MRAMs can be... 

Reliability, performance, and energy consumption are among the most important constraints that should be satisfied in modern processors design. More than 60% of the chip area is occupied by on-chip SRAM memories and they not only contribute in a large fraction of energy consumption, but also are the most error-prone components. Radiation-induced soft errors in on-chip memories are a major concern in modern processors design. Although Single Event Upsets (SEUs) have been known to be the main concern regarding SRAM memory reliability over the past decades, with the continued downscaling of technology, the occurrence rate of Multiple-Bit Upsets (MBUs) is comparable to that of SEUs in today’s... 

Recent advances in Very-Large-Scale Integration (VLSI) technologies have enabled designers to integrate a large number of Processing Elements (PEs) on a single die. According to International Technology Roadmap for Semiconductors (ITRS), the number of PEs will reach 5000 on a single die in 2021. Although the main achievements of such rapid advancement in chips are high processing speed, shrinkage of technology size has made chips highly sensitive to different challenges. Networks on chip (NoCs), as an example of these systems, are not exempted from these challenges. Crosstalk fault is one of the major fault resources in NoCs. Crosstalk faults occur due to coupling capacitances between... 

In this thesis, we intend to propose low cost SED-tolerant techniques for different compo­ nents of embedded processors core including data path components such as register file and ALU as well as control path components such as control unit. Since the reliability es­ timation is the essential step in design of a fault-tolerant system, we propose fast and accu­ rate analytical soft error rate (SER) estimation techniques in Section 4. The proposed techniques have the ability to measure: 1) the SER of a design; 2) the SER of each indi­ vidual gate and FF, and 3) the SER of a specific path in the design. Using such infor­ mation, designers can selectively protect the vulnerable parts... 

The aggressive device scaling and exponential increase in transistor counts on a chip have increasingly made the modern integrated circuits more susceptible to soft errors. Soft errors are caused by strikes from energetic particles such as neutrons and alpha particles. These errors are making a significant impact in the microelectronics industry. An essential step to design a highly reliable digital system with minimal performance and power penalty is Soft Error Rate (SER) estimation of system components.We propose a very fast and accurate analytical approach to estimate the overall SER and to identify the most vulnerable gates, flip-flops, and paths of a circuit. Our proposed approach fully... 

When multicore processors entered in industry and parallel processing became popular, most challenges have started. Some of the challenges include binding and time sharing of an application with deadline meating constraint. Another important challenge is that, these kinds of processors become more susceptible to transient faults. Among solutions to the mentioned challenges, virtualization which was one of the well known ones becomes applicable again because of some of its advantages such as flexibility, high abstraction and low cost implementation. But this technology has some drawbacks too. It can make system complex and leads to memory and performance overhead. Constructing a reliable... 

Ever increasing use of embedded systems has made them an inevitable part of human life. In 2006, more than 76% of fabricated microprocessors were used in embedded systems. On the other hand, the most important applications for embedded systems are the safty-critical applications and failure in these systems can ba catastrophic. Nowadays, the probability of transient faults has been increasing 8% with coming of the new age of fabrications. So, dependability has been an important concern for the desginers. Control flow checking has been one of the most important ways of avoding failurs.in this thesis a software control flow checking method has been introduced. This mechanism is based on branch... 

Reconfiguration, short development time and low cost have made Field Programmable Gate Arrays (FPGAs) an appealing option for digital circuit designers. Meanwhile, the occurrence of Single Event Upset (SEU) in configuration memory of SRAM-based FPGAs can change the implemented design inside the FPGA chip. Assessing reliability of FPGA-based designs against pernicious effects of SEU has long been a challenge. Several approaches can be used to evaluate the reliability of a given design. One important approach is injecting fault into the configuration memory of a device.The existing fault injection frameworks are specific in the property e.g. providing speed only, neglecting other properties of...