Sharif Digital Repository

Ever Increasing use of commercial off-the-shelf (COTS) processors to reduce cost and time to market in embedded systems has brought significant challenges in error detection and recovery methods employing in such systems. This paper presents a software based control flow error detection and correction technique, so called branch TMR (BTMR), suitable for use in COTS-based embedded systems. In BTMR method, each branch instruction is triplicated and a software interrupt routine is invoked to check the correctness of the branch instruction. During the execution of a program, when a branch instruction is executed, it is compared with the second redundant branch in the interrupt routine. If a... 

A wireless sensor network with a large number of small sensor nodes can be used as an effective tool for gathering data in various situations. Energy is a critical resource in wireless sensor networks and system lifetime needs to be prolonged through the use of energy-aware strategies during system operation. Routing protocols in WSNs might differ depending on the application and network architecture. Many routing protocols have been specifically designed for WSNs where energy awareness is an essential design issue. The aim of this paper is to evaluate the efficiency of a routing protocol named directed flooding which is a fault-tolerant and energy efficient routing protocol for wireless... 

Multicore processors are becoming popular in safety-critical applications. A series of these applications comprises of kernels where inexact computations may produce results within the boundary of sufficient quality though, for which the reliability should stay at the maximum possible level. Intrinsic core-level redundancy in multicore processors can be leveraged to achieve the desired reliability level in form of N-modular redundancy (NMR). While NMR provides a proactive means of reliability for critical systems, it has two main drawbacks: Increase in the area and energy consumption that are both limiting factors in the embedded systems. This paper presents a software-based method to... 

The switch level is an abstraction level between the gate level and the electrical level, offers many advantages. Switch level simulators can reliably model many important phenomena in CMOS circuits, such as bi-directional signal propagation, charge sharing and variations in driving strength. However, the fault simulation of switch level models is more time-consuming than gate level models. This paper presents a method for fast fault emulation of switch level circuits using FPGA chips. In this method, gates model switch level circuits and we can emulate mixed gate-switch level models. By the use of this method, FPGA chips can be used to accelerate the fault injection campaigns into switch... 

Erasure codes are applied in storage systems including both Hard Disk Drive (HDD) and Solid State Disk (SSD) to protect arrays of disks against failures. Applying these codes in SSD-based systems incurs additional number of Program/Erase (P/E) cycles on each disk, which may accelerate the wear-out of disks. This means that while erasure codes improve reliability of SSD-based systems, they impose a side-effect that may degrade reliability as the number of P/E cycles increases. This paper investigates the benefit and side-effect of erasure codes on reliability of SSD-based systems. The investigation attempts to find out the parameters which improve/damage reliability. This study has been... 

This paper presents an analytical approach to estimate the speedup in a simulation-emulation cooperation environment. The speedup of this approach as compared with the speedup of a pure simulation is analyzed. Also, an analysis of the speedup is given when different types of application instructions are utilized. The analysis is based on using both Verilog and VHDL. The results show that when only the simulation part of the simulation-emulation co-operation is used, the speedup is higher, than when the pure simulation is used. The total speedup is also depended on the type of application instructions and the communication cycle time between the simulator and the emulator. © 2002 IEEE  

This paper proposes a Low Cost circuit level Fault Detection technique called LCFD for a one-bit Full Adder (FA) as the basic element of adder circuits. To measure the fault detection coverage of the proposed technique, we conduct an exhaustive circuit level fault injection experiment on all susceptible nodes of a FA. Experimental results show that the LCDF technique can detect about 83% of injected faults while having only about 40% area and 22% power consumption overheads. In the LCDF technique, the fault detection latency does not affect the latency of the FA, since the error detection is done in parallel with the addition  

Energy innovation is essential for tackling climate change. However, an established set of indicators, that can support policy makers in their design of policy mixes, has not been developed for evaluating the performance of energy innovation systems. The purpose of this study is, therefore, to list and classify a large set of indicators of the performance of energy innovation systems at sectoral and technological levels. 120 listed indicators are evaluated using four usefulness criteria, demonstrating significant weaknesses in the available indicators. The indicators are also classified according to an innovation process categorization to see if they cover all aspects of an innovation system... 

This paper analyzes the problem of transient-error recovery of several protecting techniques used in fault-tolerant cache memories. In this paper, reliability and mean-time-to-failure (MTTF) equations for several protecting techniques are derived and estimated. The results of the considered techniques are compared with those of cache memories without redundancies and with only parity codes in both tag and data arrays of caches. Depending on the error rate under which a cache memory will operate, and the size of the cache memory, one of the analyzed cases could be used. If the transient-error rate is very small or the size of cache memory is relatively small, then a protected with only single... 

Spin-Transfer Torque RAM (STT-RAM) is a promising alternative to SRAM for implementing on-chip L2 and L3 caches. One of the most critical challenges in STT-RAM is reliability due to limited write endurance, which results in insufficient lifetime, as well as various types of errors. Previous studies have focused on either presenting various cache architectures/management techniques to improve the lifetime of STT-RAM caches or utilizing different Error Correcting Codes (ECCs) to protect against the permanent and transient errors. However, there is no quantitative analysis in the literature to determine the impact of ECCs on the lifetime of the STT-RAM caches. This paper formulates this impact... 

The use of Solid State Drives (SSDs) has been increased in storage systems due to high performance and low power consumption. However, some inherent properties of SSDs result in different behavior for SSDs in comparison with Hard Disk Drives (HDDs). As an inherent property, the Bit Error Rate (BER) of SSDs increases, when the number of Program/Erase (P/E) cycles arises. This increment leads to two effects in an array of SSDs during its operation: (1) different BER on different SSDs of the system (SSD-variant BER), and (2) different BER in different time moments (time-variant BER). With respect to these two effects, the reliability evaluation of SSD-based RAIDs would be different from... 

The ODYSSEY design methodology has been recently introduced as a viable solution to the increasing design complexity problem in the ASICs. It is an object-oriented design methodology which models a system in terms of its constituting objects and their corresponding method calls. Some of these methods are implemented in hardware; others are simply executed by a general purpose processor. One fundamental element of this methodology is a network on chip that implements method invocation for hardware-based method calls. However this network is prone to faults, thus errors on it may result into system failure. In this paper an architectural fault-tolerance enhancement to the ODYSSEY design... 

This paper proposes a Numeral-Based Crosstalk Avoidance Coding (NB-CAC) to protect communication channels of Network-on-Chips (NoCs) against crosstalk faults. The NB-CAC scheme produces codewords without bit patterns '101' and '010' to eliminate harmful transition patterns from NoC channels. This is done by the use of a new numeral system proposed in the paper. Using the proposed numeral system, the NB-CAC scheme 1) can be utilized in NoC channels with any arbitrary width, and 2) can be implemented with low area, power, and timing overheads. VHDL and SPICE simulations have been carried out for a wide range of channel widths to evaluate delay, area, and power consumption of the NB-CAC codecs.... 

Data transmission in Network-on-Chips (NoCs) is a serious problem due to crosstalk faults happening in adjacent communication links. This paper proposes an efficient flow-control method to enhance the reliability of packet transmission in Network-on-Chips. The method investigates the opposite direction transitions appearing between flits of a packet to reorder the flits in the packet. Flits are reordered in a fixed-size window to reduce: 1) the probability of crosstalk occurrence, and 2) the total power consumed for packet delivery. The proposed flow-control method is evaluated by a VHDL-based simulator under different window sizes and various channel widths. Simulation results enable NoC... 

This paper presents a cost-efficient technique to jointly use circuit- and architecture-level techniques to protect an embedded processor's register file against soft errors. The basic idea behind the proposed technique is robust register caching (RRC), which creates a cache of the most vulnerable registers within the register file in a small and highly robust cache memory built from circuit-level single-event-upset-protected memory cells. To guarantee that the most vulnerable registers are always stored in the robust register cache, the average number of read operations during a register's lifetime is used as a metric to guide the cache replacement policy. A register is vulnerable to soft... 

The severity of timing delay in the communication channels of Network on Chip (NoC) depends on the transition patterns appearing on the wires. An analytical model can estimate the timing delay in NoC channels in the presence of crosstalk faults. However, recently proposed analytical model does not have enough accuracy and is based on 3-wire delay model. In this paper, an Accurate Crosstalk Model (ACM) based on 5-wire delay model is proposed to estimate the delay of communication channels in the presence of crosstalk faults. ACM is more accurate due to considering more wires in the delay model and also considering the overlaps between locations of transition patterns  

Migration to Three Dimensional Integrated Circuits (3D ICs) can provide higher scalability, higher throughput, and lower power consumption with respect to Two Dimensional Integrated Circuits (2D ICs). Also, the latency bottleneck of interconnections in 2D ICs is efficiently solved in 3D ICs. This is due to the use of Through-Silicon-Vias (TSVs) in the communication structure of 3D ICs. TSVs are among the efficient fabrication mechanisms that connect stacked layers in 3D ICs. However, proximity and large size of TSVs make them highly prone to crosstalk faults. Crosstalk faults can cause mutual undesired influences between TSVs and thus seriously threat the reliability of data transfer on... 

Scratchpad memories (SPMs) are widely employed inmulticore embedded processors. Reliability is one of the major constraints in the embedded processor design, which is threatened with the increasing susceptibility of memory cells to multiple-bit upsets (MBUs) due to continuous technology down-scaling. This article proposes a low-cost and efficient data replication mechanism, called In-Scratchpad Memory Replication (ISMR), to correct MBUs in SPMs of multicore embedded processors. The main feature of ISMR is a smart controller, called Replication Management Unit (RMU), which is responsible for dynamically analyzing the activity of the SPM blocks at runtime and efficiently replicating the... 

FPGA-based multiprocessors, referred as softmultiprocessors, have an increasing use in embedded systems due to appealing SRAM features. More than 95% of such FPGAs are occupied by SRAM cells constructing the configuration bits. These SRAM cells are highly vulnerable to soft errors threatening the reliability of the system. This paper proposes a fault-tolerant method to detect and correct errors in the configuration bits. The main of this method is to analyze the scheduled task graph and select a subset of tasks to be replicated in multiple processors based on the utilization of the processors in different execution phases. To this end, 1) errors are detected by re-executing a subset of tasks... 

This paper presents a fault tolerant and energy efficient write-back set-associative cache, which has a heterogeneous structure. The cache architecture is based on partitioning the ways of each set into two different parts. In each set, one cache way uses SECDED code and maintains dirty blocks while the other ways employ parity bit and keep clean blocks. To evaluate the set-associative cache, SIMPLESCALAR tool and CACTI analytical model are used. The experimental results show that as the feature size decreases and the associativity increases, the energy saving of the proposed cache increases. The experimental results express that for an 8-way setassociative cache in 32nm, about 7% area and...