Loading...
Search for:
naghashi--mona
0.09 seconds
Application-aware Redundancy insertion in SIMT Processors for Improving Performance and Cost
, M.Sc. Thesis Sharif University of Technology ; Hessabi, Shaahin (Supervisor)
Abstract
Nowadays, the use of redundancy components on chips is the best method for replacing defective components on chip. This method improves yield parameter and thus reduces the manufacturing cost of a chip. However, in most of yield improvement methods, redundancy is used when the main components of a chip are defective, which is called cold redundancy. In this project, the manufacturing cost and yield parameters of chips, when using hot redundancy in SIMT processors is investigated. In the case of occurring defect on the chip, the hot redundant components are used for improving yield. Otherwise, they are used in order to improve the performance of chip. In this project, we examine systems,...
Work-in-progress: heterogeneous redundancy to address performance and cost in multi-core SIMT
, Article 2017 International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2017, 15 October 2017 through 20 October 2017 ; 2017 ; 9781450351850 (ISBN) ; Mozafari, S. H ; Hessabi, S ; Sharif University of Technology
2017
Abstract
As manufacturing processes scale to smaller feature sizes and processors become more complex, it is becoming challenging to have fabricated devices that operate according to their speciication in the irst place: yield losses are mounting [3]. © 2017 ACM
Work-in-Progress: heterogeneous redundancy to address performance and cost in multi-core SIMT
, Article Proceedings of the 12th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, CODES 2017, 15 October 2017 through 20 October 2017 ; 2017 ; 9781450351850 (ISBN) ; Mozafari, S. H ; Hessabi, S ; Sharif University of Technology
2017
Abstract
As manufacturing processes scale to smaller feature sizes and processors become more complex, it is becoming challenging to have fabricated devices that operate according to their speciication in the irst place: yield losses are mounting [3]. In this work, we investigate adding heterogeneous hot redundancy (i.e., the architecture of redundant hot cores is diferent from the baseline cores) to improve the cost and performance of multicore single-instruction, multiple-thread (SIMT) architectures. We propose to utilize x86 out of order (OoO) cores as redundancy in SIMT processors. In this case, dice with unused functional redundancies can beneit from two types of processing cores (OoO and SM)