Sharif Digital Repository

This paper presents a bandwidth enhancement technique for broadband Darlington amplifiers. A detailed analysis of the high-frequency performance of the Darlington amplifier and the effect of bandwidth enhancement is provided. A design procedure is also given for broadband feedback Darlington amplifiers with bandwidth enhancement and gain flattening. A single- and a three-stage feedback amplifier with the proposed improvements are designed and implemented in a 0.25-μm Al-GaAs-InGaAs pHEMT technology. The single-stage amplifier provides 6 ± 0.4 dB of small-signal gain in the frequency band of 1-30 GHz. The three-stage amplifier features 17.8 ± 0.8 dB of small-signal gain in the frequency band... 

This paper presents an unilateralization technique for distributed amplifiers (DAs) based on the transformer coupling between the gate and drain lines. Theoretical analysis of the DA indicates that the voltage waves in the gate and drain lines can be described by a system of linear partial differential equations. The transformer coupling between the lines allows for cancellation of the reverse transmission coefficient of the system. There is an optimal value for the coupling coefficient between the lines that unilateralizes the DA. This optimal coupling coefficient is derived in terms of the gate-drain capacitance and capacitances of the gate and drain lines. Using the proposed technique,... 

A new method for modelling and analysis of non-linearity errors caused by the capacitor mismatches and op-amp non-idealities in two-step analogue-to-digital converters (ADCs) is presented. Analytical formulas for estimation of the ADC integral non-linearity (INL) are derived. Using the proposed method, the ADC INL can be calculated in terms of the capacitor mismatches standard deviations. Therefore time-consuming Monte Carlo simulations which are conventionally used to evaluate the effect of random capacitor mismatches on the ADC linearity can be avoided. The effect of op-amp non-idealities, which are frequently examined by the circuit-level simulations, can also be evaluated using the... 

A new modeling and analysis of the nonlinearities caused by the capacitor mismatch errors in the pipeline analog-to-digital converters (ADCs) is presented. Error in each stage is modeled by an input-referred gain error and a nonlinear term. A method is proposed for calculation of the ADC integral nonlinearity (INL) from the total input referred error. Analytical expressions for estimation of the ADC INL in terms of standard deviation of random capacitor mismatch errors are derived. The proposed model is verified by system-level Monte Carlo simulations  

This paper presents the design procedure of monolithic microwave integrated circuit (MMIC) high-power amplifiers (HPAs) as well as implementation of high-efficiency and compact-size HPAs in a 0.25-μm AlGaAs-InGaAs pHEMT technology. Presented design techniques used to extend bandwidth, improve efficiency, and reduce chip area of the HPAs are described in detail. The first HPA delivers 5 W of output power with 40% power-added efficiency (PAE) in the frequency band of 8.5-12.5 GHz, while providing 20 dB of small-signal gain. The second HPA delivers 8 W of output power with 35% PAE in the frequency band of 7.5-12 GHz, while maintaining a small-signal gain of 17.5 dB. The 8-W HPA chip area is 8.8... 

The transformer-feedback (TRFB) interstage bandwidth enhancement technique for broadband multistage amplifiers is presented. Theory of the TRFB bandwidth enhancement and the design conditions for maximum bandwidth, maximally flat gain, and maximally flat group delay are provided. It is shown that the TRFB bandwidth enhancement can provide higher bandwidth compared to the conventional techniques based on reactive impedance matching networks. A three-stage low-noise amplifier (LNA) monolithic microwave integrated circuit with the TRFB between its consecutive stages is designed and implemented in a 0.1-μ m GaAs pHEMT process. The TRFB is realized by coupling between the drain bias lines of... 

In this brief, a design technique for tapered distributed low-noise amplifiers (LNAs) is presented. A circuit model is developed for gain and noise analysis of a nonuniform distributed amplifier (DA). It is shown that by optimal tapering of gate and drain transmission lines and transistors, the tapered distributed LNA can provide lower broadband average noise figure (NF) compared to a uniform DA. A proof-of-concept integrated circuit is implemented using a 0.1-μm GaAs pHEMT process. The amplifier provides average gain of 15.2 dB and 3-dB bandwidth of 43.3 GHz. The average NF of 2.3 dB and minimum NF of 2.0 dB are achieved over 2–40 GHz. The chip consumes 55 mA current from a 2-V supply. IEEE... 

A dual-band neutralization technique based on the transformer feedback between the drain and the gate of a transistor is presented. The drain and gate bias lines of the transistor are realized as multiorder LC networks. Transformer coupling between the inductors of the two networks can be used to concurrently neutralize the gate-drain capacitance of the transistor at multiple frequencies. Moreover, these frequencies can be placed close together to achieve wideband neutralization. A proof-of-concept dual-band 27/33-GHz amplifier is designed and implemented in a 0.1-μm GaAs pseudomorphic high-electron mobility transistor process. The maximum gain of the transistor at the two frequency bands is... 

In this brief, a design technique for tapered distributed low-noise amplifiers (LNAs) is presented. A circuit model is developed for gain and noise analysis of a nonuniform distributed amplifier (DA). It is shown that by optimal tapering of gate and drain transmission lines and transistors, the tapered distributed LNA can provide lower broadband average noise figure (NF) compared to a uniform DA. A proof-of-concept integrated circuit is implemented using a 0.1-μm GaAs pHEMT process. The amplifier provides average gain of 15.2 dB and 3-dB bandwidth of 43.3 GHz. The average NF of 2.3 dB and minimum NF of 2.0 dB are achieved over 2-40 GHz. The chip consumes 55 mA current from a 2-V supply. ©... 

In this research, we investigate a three-stage supply chain with one supplier, several manufacturers and multiple retailers where the supplier provides a common raw material to each manufacturer, who in turn uses a single stage production facility to convert it into final products that are delivered at fixed lot sizes to retailers. An integrated economic procurement, production, and delivery model is developed whose objective is to find the common production cycle length, production sequences of final products at manufacturers and delivery frequencies of final products to retailers minimizing the total costs of considered supply chain. We propose an analytical solution procedure and an... 

Theoretical stability analysis of broadband cascode amplifiers at high frequencies is presented. The stability of the amplifier in the presence of parasitic inductive components is thoroughly investigated. It is shown that the stability can be improved by inserting a series resistance in the gate of common-gate device of the cascode amplifier. To ensure stability, the gate resistance should be selected within specific ranges that are derived analytically. Based on the insights provided by the analyses, several practical design guidelines are given to improve the stability of high-frequency broadband cascode amplifiers. Finally, the derived results are adopted in stabilisation of an X-band... 

This paper presents a harmonic termination technique for single-and multi-band high-efficiency class-F monolithic microwave integrated circuit (MMIC) power amplifiers (PAs). The harmonic termination network (HTN), realized with the minimum possible number of elements, can be used to terminate an arbitrary number of harmonics in a single-band PA or harmonics of multiple frequencies in a concurrent multi-band PA. The drain and gate bias lines are embedded in the HTNs to obviate the need for RF chokes and reduce the chip area. A single-and a dual-band MMIC PA are designed using the proposed technique and implemented in a 0.25-μm AlGaAs-InGaAs pHEMT technology. The single-band 5.5-GHz PA... 

Design techniques to enhance bandwidth and linearity of broadband multistage low-noise amplifiers (LNAs) are presented. A feedback amplifier circuit is proposed to compensate for transistor gain roll-off with frequency in other amplifier stages and extend overall bandwidth. Moreover, a transistor width tapering in a multistage LNA is applied to improve linearity. These techniques are adopted in a three-stage monolithic microwave integrated circuit (MMIC) LNA implemented in a 0.1-μm GaAs pHEMT process. The LNA features 18-43 GHz bandwidth, 21.6 dB average gain, and 1.8-2.7 noise figure (NF). It exhibits output 1-dB compression point of 11.5 dBm at 30 GHz and consumes 70 mA bias current from a... 

Let H be a group. The co-maximal graph of subgroups of H, denoted by Γ(H), is a graph whose vertices are non-trivial and proper subgroups of H and two distinct vertices L and K are adjacent in Γ(H) if and only if H = LK. In this paper, we study the connectivity, diameter, clique number, and vertex chromatic number of Γ(H). For instance, we show that if Γ(H) has no isolated vertex, then Γ(H) is connectedwith diameter at most h. Also, we characterize all finite groupswhose co-maximal graphs are connected. Among other results, we show that if H is a finitely generated solvable group and Γ(H) is connected, and moreover, the degree of a maximal subgroup is finite, then H is finite. Furthermore,... 

In this paper a theoretical comparison between the performance of switched-capacitor (SC) and switched-current (SI) pipeline analog-to-digital converters (ADCs) is presented. Power dissipation and die area of SC and SI implementations are compared based on linearity and noise constraints. It is shown that if nonlinearity errors of the class AB SI ADCs are removed by calibration, their performance prevails that of the SC ADCs. Also it is shown that class AB SI ADCs occupy less die area than SC ADCs for a given resolution. © 2007 IEEE  

In this paper a general method for system level prediction of INL in pipeline analog to digital converters is presented. For each stage of the ADC, a new error model consisting of an input referred gain error and a nonlinear term is introduced. An analytic method to calculate INL from all error sources is presented. INL model for a switched-capacitor implementation is also presented. ©2006 IEEE  

A large-signal analysis of sub-harmonic parametric oscillations in Power Amplifiers (PAs) is presented in this paper. Simplified models for current-voltage and channel charge characteristics of short-channel pseudomorphic High Electron Mobility Transistors (pHEMTs) are adopted to investigate the effects of the device transconductance and gate-source capacitance nonlinearities on the amplifier stability. A 5-W Ku-band PA is designed to demonstrate the application of the presented analysis. MMIC PA is implemented in a 0.25-μm GaAs pHEMT process. According to the measurements, the PA provides 37.5 dBm (5.6 W) of output power, 36% of Power Added Efficiency (PAE), and small-signal gain of 18 dB...