Sharif Digital Repository

Fontan operation is a final palliative surgical treatment for patients with a single ventricle (SV) physiology. One of the common disadvantages of Fontan operation is to generate a non-pulsatile flow instead of the normal pulsatile flow produced by contraction of the ventricle. Theoretically, in SV patients, maintaining the antegrade flow through pulmonary valve can produce flow pulsatility in the right and left pulmonary arteries. However, it not only increases the energy loss in the Fontan of total cavopulmonary pathway (TCPC), but also imposes an extra load on pulmonary arteries as well as the ventricle. In this study, the potential capability of pulmonary valve of the patient that can be... 

Single-ventricle anomaly is a hereditary heart disease that is characterized by anatomical malformations. The main consequence of this malformation is desaturated blood flow, which without proper treatment increases the risk of death. The classical treatment is based on a three-stage palliative procedure which should begin from the first few days of patient’s life. The final stage is known as Fontan procedure, in which inferior vena cava is directly connected to pulmonary arteries without going through the ventricle. This connection is called total cavopulmonary connection (TCPC). After surgery, the single ventricle supplies adequate and saturated systemic blood flow to the body; however,... 

Numerous analytical performance models have been proposed for deterministic wormhole-routed mesh networks while only a single model, to our best knowledge, has been suggested for fully adaptive wormhole routing in mesh interconnection networks. This paper proposes a new and accurate analytical performance model for fully adaptive wormhole-routed mesh networks. Simulation results show that unlike the previously proposed model which is only accurate in light traffic loads, this model can be used for the performance analysis of almost all traffic loads. © 2007 Elsevier B.V. All rights reserved  

Mesh-based interconnection networks are the most popular inter-processor communication infrastructures used in current parallel supercomputers. Although many analytical models of n-D torus interconnection networks have been reported in the literature over the last decade, few analytical models have been proposed for the 2-D mesh case (and not for the general n-D mesh network) using inaccurate approximations as they have not fully incorporated the asymmetry effects of the mesh topology, in order to reduce the model complexity. There has not been reported, to the best of our knowledge, a performance model that can deal with the n-D mesh network. To fill this gap, in this paper, we propose the... 

Mesh-based interconnection networks are the most popular inter-processor communication infrastructures used in current parallel supercomputers. Although many analytical models of n-D torus interconnection networks have been reported in the literature over the last decade, few analytical models have been proposed for the 2-D mesh case (and not for the general n-D mesh network) using inaccurate approximations as they have not fully incorporated the asymmetry effects of the mesh topology, in order to reduce the model complexity. There has not been reported, to the best of our knowledge, a performance model that can deal with the n-D mesh network. To fill this gap, in this paper, we propose the... 

Concurrent signatures allow two entities to generate two signatures in such a way that both signatures are ambiguous till some information is revealed by one of the parties. This kind of signature is useful in auction protocols and in a wide range of scenarios in which involving participants are mutually distrustful. In this study, to have quantum-attack-resistant concurrent signatures as recommended by National Institute of Standards and Technology (NISTIR 8105), the first concurrent signature scheme based on coding theory is proposed. Then, its security is proved under Goppa Parameterized Bounded Decoding and the Goppa Code Distinguishing assumptions in the random oracle model. In... 

While the Control Flow Checking (CFC) methods are using the ordinary instruction set and general Arithmetic and Logic Unit (ALU) features to protect the programs against the transient faults, this paper presents a new kind of CFC method, called feature specific CFC. The idea behind this method is using a specific internal hardware in modern processors which provides the ability to monitor internal various parameters of the program. This method is a pure software method and the external hardware overhead is zero. Other overheads have been measured experimentally by executing the workloads on a Pentium system. The execution time overhead is between 42% and 67% and the program size overhead is... 

This paper presents a software-based error detection scheme called enhanced committed instructions counting (ECIC) for embedded and real-time systems using commercial off-the-shelf (COTS) processors. The scheme uses the internal performance monitoring features of a processor, which provides the ability to count the number of committed instructions in a program. To evaluate the ECIC scheme, 6000 software induced faults are injected into a 32-bit Pentium® processor. The results show that the error detection coverage varies between 90.52% and 98.18%, for different workloads. © 2004 Elsevier Ltd. All rights reserved  

This paper presents a behavioral-based error detection technique called control flow checking by execution tracing (CFCET) to increase concurrent error detection capabilities of commercial off-the-shelf (COTS) processors. This technique traces the program jumps graph (PJG) at run-time and compares it with the reference jumps graph to detect possible violations caused by transient faults. The reference graph is driven by a preprocessor from the source program. The idea behind the CFCET is based on using an external watchdog processor (WDP) and also the internal execution tracing feature available in COTS processors to monitor the addresses of taken branches in a program, externally. This is... 

To enhance the error detection capability in COTS (commercial off-the-shelf) -based design of safety-critical systems, a new hardware-based control flow checking (CFC) technique will be presented. This technique, Control Flow Checking by Execution Tracing (CFCET), employs the internal execution tracing features available in COTS processors and an external watchdog processor (WDP) to monitor the addresses of taken branches in a program. This is done without any modification of application programs, therefore, the program overhead is zero. The external hardware overhead is about 3.5% using an Altera Flex 10K30 FPGA. For different workload programs, the execution time overhead and the error... 

The Fontan surgery is performed on patients with a single ventricle heart defect to prevent the combination of highlyoxygenated and poorly-oxygenated blood. Blood flow in total cavopulmonary connection (TCPC) which culminates an ordinary Fontan operation is practically steady-state but this flow is not appropriate for respiratory systems. This article investigates an approach in Fontan surgery that has been recently proposed in order to make the pulmonary blood flow pulsating. Moreover, for investigating the compliance of vessels and its effects on blood flow in TCPC, we have used the FSI (Fluid Structure Interaction) method as well as rigid wall assumption for comparison purposes. Our TCPC... 

Increasing use of commercial off-the-shelf (COTS) superscalar processors in industrial, embedded, and real-time systems necessitates the development of error detection mechanisms for such systems. This paper presents an error detection scheme called Committed Instructions Counting (CIC) to increase error detection in such systems. The scheme uses internal Performance Monitoring features and an external watchdog processor (WDP). The Performance Monitoring features enable counting the number of committed instructions in a program. The scheme is experimentally evaluated on a 32-bit Pentium® processor using software implemented fault injection (SWIFI). A total of 8181 errors were injected into... 

Proxy ring (anonymous proxy) signatures allow an entity to delegate its signing capability to a group of entities (proxy group) such that only one of the members in the proxy group can generate a proxy signature on behalf of the delegator, while privacy of the proxy signer is protected. Identity-based versions of proxy ring signatures employ identity strings in place of randomly generated public keys. Our contribution is twofold. First, we formalize a security model for identity-based proxy ring signatures. We note that there exists no formal security model for identity-based proxy ring signatures prior to our work. Second, we present the first provably secure identity-based proxy ring... 

Identity-based proxy ring signature concept was introduced by Cheng et al. in 2004. This primitive is useful where the privacy of proxy signers is required. In this paper, the first short provably secure identity-based proxy ring signature scheme from RSA assumption has been proposed. In addition, the security of the proposed scheme tightly reduces to the RSA assumption, and therefore, the proposed scheme has a proper advantage in security reduction compared to the ones from RSA. The proposed scheme not only outperforms the existing schemes in terms of efficiency and practicality, but also does not suffer from the proxy key exposure attack due to the use of the sequential aggregation... 

Proxy signatures allow an entity to delegate its signing capability to a proxy which can sign messages on behalf of the delegator. We examine identity-based versions of proxy signatures which employ identity strings in place of randomly generated public keys. First, we give a new generic construction of identity-based proxy signatures from identity-based standard signatures and show that our generic construction is secure if the underlying identity-based standard signature is secure. In addition, we present the first identity-based proxy signature from Rivest, Shamir and Adleman (RSA), secure under the one-wayness of RSA in the random oracle model. We should highlight that the proxy key... 

The notion of identity-based proxy signature with message recovery feature has been proposed to shorten identity-based proxy signatures and improve their communication overhead because signed messages are not transmitted with these kinds of signatures. There are a few schemes for this notion: the schemes of Singh and Verma and Yoon et al. Unfortunately, Tian et al., by presenting two forgery attacks, show that Singh and Verma scheme is not secure, and also, the scheme of Yoon et al. does not support provable security. The contributions of this paper are twofold. First, we review the scheme by Yoon et al. and discuss why it does not have message recovery property, and consequently, it is not... 

Lin, Hwang and Chang (2003) have proposed an electronic-voting scheme which can be utilised in large-scale elections, and claimed that it detects double voting. In this article, by presenting an attack, we show that voters can successfully vote more than once without being detected. Then, we propose a new modified scheme based on the Lin, Hwang and Chang's (2003) scheme with the same efficiency to solve this weakness and analyse its security. © 2008, Inderscience Publishers  

This paper presents an experimental evaluation of the effectiveness of the Master/Checker (M/C) architecture in a 32-bit Pentium® processor system using both power-supply disturbance (PSD) fault injection and software-implemented fault injection (SWIFI) methods. A total of 6000 faults were injected in the Master processor to measure the error detection coverage of the Checker processor. The results of the experiments with PSD fault injection show that the error detection coverage of the M/C architecture is about 66.13%, which is not quite effective. This low coverage depends on the high rate of Master processor hangs because of voltage fluctuation. The coverage increased to about 99.73% when... 

Increasing use of commercial off-the-shelf (COTS) superscalar processors in industrial, embedded, and real-time systems necessitates the development of error detection mechanisms for such systems. This paper presents an error detection scheme called Committed Instructions Counting (CIC) to increase error detection in such systems. The scheme uses internal Performance Monitoring features and an external watchdog processor (WDP). The Performance Monitoring features enable counting the number of committed instructions in a program. The scheme is experimentally evaluated on a 32-bit Pentium® processor using software implemented fault injection (SWIFI). A total of 8181 errors were injected into...