Sharif Digital Repository

Due to the growing demand for large memories, using emerging technologies such as Phase Change Memories (PCM) are inevitable. PCM with appropriate scalability, power consumption and multiple bits per cell storage capability is a probable candidate for substituting DRAM. Although storing multiple bits per cell seems to be a rational response to large memory demands, there is a significant problem to achieve this goal. Resistance drift problem is an important reliability concern that is coupled to a multi-level cell PCM (MLC PCM) memory system. In this paper, we propose a memory system architecture that, by exploiting the benefits of compression, converts resistance drift prone blocks to drift... 

In this paper, we propose a reconfigurable NoC in which a customized topology for a given application can be implemented. In this NoC, the nodes are grouped into some clusters interconnected by a reconfigurable communication infrastructure. The nodes inside a cluster are connected by a fixed topology. From the traffic management perspective, this structure benefits from the interesting characteristics of the mesh topology (efficient handling of local traffic where each node communicates with its neighbors), while avoids its drawbacks (the lack of short paths between remotely located nodes). We then present a design flow that maps the frequently communicating tasks of a given application into... 

In this paper, a parallel algorithm for computing the roots of a given polynomial of degree n on a ring of processors is proposed. The algorithm implements Durand-Kerner's method and consists of two phases: initialisation, and iteration. In the initialisation phase all the necessary preparation steps are realised to start the parallel computation. It includes register initialisation and initial approximation of roots requiring 3n - 2 communications, 2 exponentiation, one multiplications, 6 divisions, and 4n - 3 additions. In the iteration phase, these initial approximated roots are corrected repeatedly and converge to their accurate values. The iteration phase is composed of some iteration... 

In this paper, a parallel algorithm for computing the roots of a given polynomial of degree n on a ring of processors is proposed. The algorithm implements Durand-Kerner's method and consists of two phases: initialization, and iteration. In the initialization phase all the necessary preparation steps are realized to start the parallel computation. It includes register initialization and initial approximation of roots requiring 3n-2 communications, 2 exponentiation, one multiplications, 6 divisions, and 4n-3 additions. In the iteration phase, these initial approximated roots are corrected repeatedly and converge to their accurate values. The iteration phase is composed of some iteration... 

Although several analytical models have been proposed in the literature for binary n-cubes with deterministic routing, most of them have not included the effects of virtual channel multiplexing on network performance. The only mathematical model for deterministic wormhole routing in hypercubes with virtual channels was proposed in [Y. Boura, Design and Analysis of Routing Schemes and Routers for Wormhole-routed Mesh Architectures, Ph.D. Thesis, Department of Computer Science and Engineering, Pennsylvania State University, 1995] which uses complex combinatorial analysis with a computation time of O(N = 2n) for an n-dimensional hypercube. This paper proposes a new and simple analytical model... 

The mesh structure has been used as the underlying topology for many practical multicomputers, and has been extensively studied in the past. In this paper, we investigate some topological properties of meshes. In particular, we study the problem of finding the number of nodes located at a given distance from a given node (surface area) and the number of nodes located within a given distance from a given node (volume), and have derived some expressions calculating these numbers  

Several studies have examined the relative performance merits of the torus and hypercube taking into account the channel bandwidth constraints imposed by implementation technology. While the torus has been shown to outperform the hypercube under the constant wiring density constraint, the opposite conclusion has been reached when the constant pin-out constraint is considered. However, all these studies have assumed deterministic routing and have not taken into account the internal hardware cost of routers. This paper re-examines the performance merits of the torus and hypercube using both fully-adaptive and deterministic routing strategies. Moreover, it uses a new cost model which takes into... 

In this paper, a parallel algorithm for computing the roots of a given polynomial of degree n on a ring of processors is proposed. The algorithm implements Durand-Kerner's method and consists of two phases: initialisation, and iteration. In the initialisation phase all the necessary preparation steps are realised to start the parallel computation. It includes register initialisation and initial approximation of roots requiring 3n - 2 communications, 2 exponentiation, one multiplications, 6 divisions, and 4n - 3 additions. In the iteration phase, these initial approximated roots are corrected repeatedly and converge to their accurate values. The iteration phase is composed of some iteration... 

Networks-on-Chip (NoCs) play an important role in the performance of Chip Multi-Processors (CMPs). Providing the desired performance under heavy traffics imposed by some applications necessitates NoC routers to have a large number of Virtual Channels (VCs). Increasing the number of VCs, however, will add to the delay of the critical path of the arbitration logic, and hence restricts the clock frequency of the router. In order to make it possible to enjoy the benefits of having many VCs and keep the clock frequency as high as that of a low-VC router, we propose Parallel Pseudo-Round-Robin (P2R2) arbiter. Our proposal is based on processing multiple groups of requests in parallel. Our... 

Core specialization is a promising solution to the dark silicon challenge. This approach trades off the cheaper silicon area with energy-efficiency by integrating a selection of many diverse application-specific cores into a single billion-transistor multicore chip. Each application then activates the subset of cores that best matches its processing requirements. These cores act as a customized application-specific CMP for the application. Such an arrangement of cores requires some special on-chip inter-core communication treatment to efficiently connect active cores. In this paper, we propose a reconfigurable network-on-chip that leverages the routers of the dark portion of the chip to... 

Topology of a mobile wireless sensor/ad hoc network is prone to link breakages due to node mobility which compels the periodic re-construction of the topology in so called ""hello"" intervals. The problem addressed in this paper is determining the maximum ""hello"" interval preserving the connectivity of a homogeneous topology with high probability. In order to study the optimum ""hello"" interval, statistical topology lifetime (STL) is formally defined as a value of ""hello"" interval that ensures statistical connectivity with a given threshold. Temporal properties of the topology are studied based on two phenomena; one concerning a connectivity phase transition with time and the other one...