WiP: Floating xy-yx: An efficient thermal management routing algorithm for 3d nocs

, Article 16th IEEE International Conference on Dependable, Autonomic and Secure Computing, IEEE 16th International Conference on Pervasive Intelligence and Computing, IEEE 4th International Conference on Big Data Intelligence and Computing and IEEE 3rd Cyber Science and Technology Congress, DASC-PICom-DataCom-CyberSciTec 2018, 12 August 2018 through 15 August 2018 ; 2018 , Pages 730-735 ; 9781538675182 (ISBN) Safari, M ; Shirmohammadi, Z ; Rohbani, N ; Farbeh, H ; Sharif University of Technology

Institute of Electrical and Electronics Engineers Inc 2018

Abstract

3D Network-on-Chips (3D NoCs) have higher scalability, higher throughput, and lower power consumption over 2D NoCs. However, the reliability of data transfer in 3D NoCs is seriously threatened by thermal problems. This is due to poor heat dissipation, inappropriate traffic distribution, and cooling restriction for layers away of the chip heat-sink in 3D NoCs. To solve this problem, this paper proposes an efficient deadlock-free and traffic-And thermal-Aware routing algorithm, called Floating XY-YX. The main idea behind Floating XY-YX routing algorithm is twofold: 1) to use XY and YX routing algorithms in consecutive layers in dessicate form, and 2) to evenly load the traffic, which is...

PVMC: Task mapping and scheduling under process variation heterogeneity in mixed-criticality systems

, Article IEEE Transactions on Emerging Topics in Computing ; Volume 10, Issue 2 , 2022 , Pages 1166-1177 ; 21686750 (ISSN) Bahrami, F ; Ranjbar, B ; Rohbani, N ; Ejlali, A ; Sharif University of Technology

IEEE Computer Society 2022

Abstract

Embedded Systems (ESs) have migrated from special-purpose hardware to commodity hardware. These systems have also tended to Mixed-Criticality (MC) implementations, executing applications of different criticalities upon a shared platform. Multi-cores, which are commonly used to design MC Systems (MCSs), bring out new challenges due to the Process Variation (PV). Power and frequency asymmetry affects the predictability of ESs. In this work, variation-aware techniques are explored to not only improve the reliability of MCSs, but also aid the scheduling and energy saving of them. We leverage the Core-to-Core (C2C) variations to protect high-criticality tasks and provide full service for a high...

LETHOR: a thermal-aware proactive routing algorithm for 3D NoCs with less entrance to hot regions

, Article Journal of Supercomputing ; Volume 78, Issue 6 , 2022 ; 09208542 (ISSN) Safari, M ; Shirmohammadi, Z ; Rohbani, N ; Farbeh, H ; Sharif University of Technology

Springer 2022

Abstract

Although many Dynamic Thermal Management (DTM) techniques are employed to overcome thermal problems in 3D NoCs, none of them consider temperature information of all nodes of a layer at the same time, so that they cannot reduce the temperature of the network properly.To overcome this problem, this paper proposes an efficient proactive thermal-aware routing algorithm, called Less Entrance to Hot Regions (LETHOR), to keep the NoC temperature lower than a predefined thermal limit. LETHOR routes the network packets based on the temperature information of all nodes in the layers instead of considering only the neighbor nodes in each hop. To this aim, LETHOR introduces a Hot Region in each layer...

A fault-tolerant and energy-aware mechanism for cluster-based routing algorithm of WSNs

, Article Proceedings of the 2015 IFIP/IEEE International Symposium on Integrated Network Management, IM 2015, 11 May 2015 through 15 May 2015 ; May , 2015 , Pages 659-664 ; 9783901882760 (ISBN) Hezaveh, M ; Shirmohammdi, Z ; Rohbani, N ; Miremadi, S. G ; Sharif University of Technology

Institute of Electrical and Electronics Engineers Inc 2015

Abstract

Wireless Sensor Networks (WSNs) are prone to faults due to battery depletion of nodes. A node failure can disturb routing as it plays a key role in transferring sensed data to the end users. This paper presents a Fault-Tolerant and Energy-Aware Mechanism (FTEAM), which prolongs the lifetime of WSNs. This mechanism can be applied to cluster-based WSN protocols. The main idea behind the FTEAM is to identify overlapped nodes and configure the most powerful ones to the sleep mode to save their energy for the purpose of replacing a failed Cluster Head (CH) with them. FTEAM not only provides fault tolerant sensor nodes, but also tackles the problem of emerging dead area in the network. Our...

PVMC: task mapping and scheduling under process variation heterogeneity in mixed-criticality systems

, Article IEEE Transactions on Emerging Topics in Computing ; 2021 ; 21686750 (ISSN) Bahrami, F ; Ranjbar, B ; Rohbani, N ; Ejlali, A. R ; Sharif University of Technology

IEEE Computer Society 2021

Abstract

Embedded systems have migrated from special-purpose hardware to commodity hardware. These systems have also tended to Mixed-Criticality (MC) implementations, executing applications of different criticalities upon a shared platform. Multi-core processors, which are commonly used to design MC systems, bring out new challenges due to the process variations. Power and frequency asymmetry affects the predictability of embedded systems. In this work, variation-aware techniques are explored to not only improve the reliability of MC systems, but also aid the scheduling and energy saving of them. We leverage the core-to-core (C2C) variations to protect high-criticality tasks and provide full service...

Power-efficient and aging-aware primary/backup technique for heterogeneous embedded systems

, Article IEEE Transactions on Sustainable Computing ; Volume 8, Issue 4 , 2023 , Pages 715-726 ; 23773782 (ISSN) Ansari, M ; Safari, S ; Rohbani, N ; Ejlali, A ; Al-Hashimi, B. M ; Sharif University of Technology

Institute of Electrical and Electronics Engineers Inc 2023

Abstract

One of the essential requirements of embedded systems is a guaranteed level of reliability. In this regard, fault-tolerance techniques are broadly applied to these systems to enhance reliability. However, fault-tolerance techniques may increase power consumption due to their inherent redundancy. For this purpose, power management techniques are applied, along with fault-tolerance techniques, which generally prolong the system lifespan by decreasing the temperature and leading to an aging rate reduction. Yet, some power management techniques, such as Dynamic voltage and frequency scaling (DVFS), increase the transient fault rate and timing error. For this reason, heterogeneous multicore...

A Comparative study of joint power and reliability management techniques in multicore embedded systems

, Article 3rd CSI/CPSSI International Symposium on Real-Time and Embedded Systems and Technologies, RTEST 2020, 10 June 2020 through 11 June 2020 ; 2020 Yari Karin, S ; Sahraee, A ; Saber Latibari, J ; Ansari, M ; Rohbani, N ; Ejlali, A ; Sharif University of Technology

Institute of Electrical and Electronics Engineers Inc 2020

Abstract

Low power consumption and high-reliability are often major objectives in the design of embedded systems. To reduce power consumption, embedded systems usually employ system-level power management techniques, e.g. Dynamic Voltage Scaling (DVS) and Dynamic Power Management (DPM). To achieve high reliability, embedded systems often exploit fault-tolerant techniques. Fault-tolerant techniques are in a trade-off with energy consumption, peak-power consumption, and temperature. Thus, different methods have been introduced that simultaneously consider reliability and power consumption as the system constraints. Several novel methods have been proposed in previous works to reduce the power...

A low-overhead integrated aging and SEU sensor

, Article IEEE Transactions on Device and Materials Reliability ; Volume 18, Issue 2 , 2018 , Pages 205-213 ; 15304388 (ISSN) Rohbani, N ; Miremadi, S. G ; Sharif University of Technology

Institute of Electrical and Electronics Engineers Inc 2018

Abstract

Aging has become a critical CMOS reliability issue in nanoscales. In general, the aging effect is exhibited as an increase in the delay of the combinational parts and robustness degradation of memory structures. To monitor the aging state of the combinational parts, this paper proposes an aging sensor that is combined with the flip-flops of a chip. The function of this sensor is based on monitoring the stability violation of the critical path output, before the rising edge of the clock signal. The precision of the proposed sensor is about 2.7 × of the most accurate previously presented aging sensors. This is achieved by almost 33% less area overhead compared with state-of-the-art aging...

Energy Management in Energy Harvesting Wireless Sensor Nodes

, M.Sc. Thesis Sharif University of Technology Rohbani, Nezam (Author) ; Ejlali, Ali Reza (Supervisor)

Abstract

Wireless Sensor Networks have become widespread because of their flexibility, applicability and ability to precept data with high accuracy. However, the most limiting factor in their usage is the amount of available energy in nodes since energy depletion in a node means that it is dead, therefore many efforts have been done for optimum energy management in Wireless Sensor Networks. In many cases, the key solution to prolong the network lifetime is load balancing. In this way, all the nodes will die (approximately) together and the lifetime of network will be maximized. Load balancing can be implemented in all layers from physical layer to application. It should be noted that it is not always...

Compact modeling of dynamic trap density evolution for predicting circuit-performance aging

, Article Microelectronics Reliability ; Volume 80 , 2018 , Pages 164-175 ; 00262714 (ISSN) Miura Mattausch, M ; Miyamoto, H ; Kikuchihara, H ; Maiti, T. K ; Rohbani, N ; Navarro, D ; Mattausch, H. J ; Sharif University of Technology

2018

Abstract

It is shown that a compact MOSFET-aging model for circuit simulation is possible by considering the dynamic trap-density increase, which is induced during circuit operation. The dynamic trap/detrap phenomenon, which influences the switching performance, is also considered on the basis of well-known previous results. Stress-dependent hot-carrier effect and NBTI effect, origins of the device aging, are modeled during the circuit simulation for each device by integrating the substrate current as well as by determining the oxide-field change due to the trapped carriers over the individual stress-duration periods. A self-consistent solution can be obtained only by iteratively solving the Poisson...

PF-DRAM: A precharge-free DRAM structure

, Article 48th ACM/IEEE Annual International Symposium on Computer Architecture, ISCA 2021, 14 June 2021 through 19 June 2021 ; Volume 2021-June , 2021 , Pages 126-138 ; 10636897 (ISSN); 9781665433334 (ISBN) Rohbani, N ; Darabi, S ; Sarbazi Azad, H ; Sharif University of Technology

Institute of Electrical and Electronics Engineers Inc 2021

Abstract

Although DRAM capacity and bandwidth have increased sharply by the advances in technology and standards, its latency and energy per access have remained almost constant in recent generations. The main portion of DRAM power/energy is dissipated by Read, Write, and Refresh operations, all initiated by a Precharge phase. Precharge phase not only imposes a large amount of energy consumption, but also increases the delay of closing a row in a memory block to open another one. By reduction of row-hit rate in recent workloads, especially in multi-core systems, precharge rate increases which exacerbates DRAM power dissipation and access latency. This work proposes a novel DRAM structure, called...

Cooldram: an energy-efficient and robust dram

, Article Proceedings of the International Symposium on Low Power Electronics and Design ; Volume 2023-August , 2023 ; 15334678 (ISSN); 979-835031175-4 (ISBN) Rohbani, N ; Soleimani, M. A ; Sarbazi Azad, H ; Sharif University of Technology

Institute of Electrical and Electronics Engineers Inc 2023

Abstract

DRAM is the most mature and widely-utilized memory structure as main memory in computing systems. However, energy dissipation and latency of DRAM are two of the most serious limiting factors of this technology. All DRAM main operations are initiated by a Precharge phase, which is time-consuming and power-hungry. This work proposes a novel DRAM cell access scheme that entirely eliminates Precharge phase from DRAM read, write, and refresh operations, with a very slight modification in commodity DRAM structure. The proposed DRAM design, called CoolDRAM, operates using a single extra cell row as reference cells. CoolDRAM reduces energy dissipation by about 34% on average, with a negligible area...

Reliability Improvement in Aging-sensitive Units of a Processor

, Ph.D. Dissertation Sharif University of Technology Rohbani, Nezam (Author) ; Miremadi, Ghasem (Supervisor) ; Ejlali, Alireza (Supervisor)

Abstract

Despite the advantages of shrinking transistors’ dimensions, e.g. decrease in power consumption and fabrication cost and increase in their switching speed, it has an adverse impact on some characteristics of nano-scale (less than 130nm) transistors that can reduce the system lifetime. Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) are amongst the most important adverse effects of transistor shrinkage. These two effects, are known as transistor aging, decrease the switching speed of the transistors by increasing the threshold voltage and decreasing the charge carriers’ mobility in the channel of transistors. Temperature, operating voltage, and the size of transistors have...

LAXY: a location-based aging-resilient Xy-Yx routing algorithm for network on chip

, Article IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ; Volume 36, Issue 10 , 2017 , Pages 1725-1738 ; 02780070 (ISSN) Rohbani, N ; Shirmohammadi, Z ; Zare, M ; Miremadi, S. G ; Sharif University of Technology

2017

Abstract

Network on chip (NoC) is a scalable interconnection architecture for ever increasing communication demand between processing cores. However, in nanoscale technology size, NoC lifetime is limited due to aging processes of negative bias temperature instability, hot carrier injection, and electromigration. Usually, because of unbalanced utilization of NoC resources, some parts of the network experience more thermal stress and duty cycle in comparison with other parts, which may accelerate chip failure. To slow down the aging rate of NoC, this paper proposes an oblivious routing algorithm called location-based aging-resilient Xy-Yx (LAXY) to distribute packet flow over entire network. LAXY is...

Bias temperature instability mitigation via adaptive cache size management

, Article IEEE Transactions on Very Large Scale Integration (VLSI) Systems ; Volume 25, Issue 3 , 2017 , Pages 1012-1022 ; 10638210 (ISSN) Rohbani, N ; Ebrahimi, M ; Miremadi, S. G ; Tahoori, M. B ; Sharif University of Technology

2017

Abstract

Bias temperature instability (BTI) is one of the major CMOS reliability issues in nanoscales. The main impact of BTI on SRAM memory cells is the degradation of the static noise margin (SNM), which leads to a higher susceptibility to failures. A variety of techniques for mitigating the impact of BTI on caches have been proposed at architecture level. However, their considerable overheads limit the application of such techniques. Recent studies showed that the utilization of the cache capacity widely varies from one workload to another and even within a workload. When cache utilization is low, for the majority of the cells, the same value is stored for a very long period, which significantly...

Modeling of dynamic trap density increase for aging simulation of any MOSFET circuits

, Article European Solid-State Device Research Conference, 11 September 2017 through 14 September 2017 ; 2017 , Pages 192-195 ; 19308876 (ISSN) ; 9781509059782 (ISBN) Miura Mattausch, M ; Miyamoto, H ; Kikuchihara, H ; Navarro, D ; Maiti, T. K ; Rohbani, N ; Ma, C ; Mattausch, H. J ; Schiffmann, A ; Steinmair, A ; Seebacher, E ; Sharif University of Technology

2017

Abstract

A compact aging model for circuit simulation has been developed by considering all possible trapped carriers within MOSFETs. The hot carrier effect and the N(P)BTI effect are modeled by integrating the substrate current as well as the oxide field change due to the trapped carriers. Additionally, the carriers trapped within the highly resistive drift region are included for high-voltage (HV)-MOSFET modeling. The aging model considers the dynamic trap-density increase as a function of circuit-operation time with dynamically varying stress conditions for each individual MOSFET. A self-consistent solution is obtained by iteratively solving the Poisson equation including the trap density. The...

PIPF-DRAM: Processing in precharge-free DRAM

, Article 59th ACM/IEEE Design Automation Conference, DAC 2022, 10 July 2022 through 14 July 2022 ; 2022 , Pages 1075-1080 ; 0738100X (ISSN); 9781450391429 (ISBN) Rohbani, N ; Soleimani, M. A ; Sarbazi Azad, H ; ACM Special Interest Group on Design Automation (SIGDA); IEEE CEDA ; Sharif University of Technology

Institute of Electrical and Electronics Engineers Inc 2022

Abstract

To alleviate costly data communication among processing cores and memory modules, parallel processing-in-memory (PIM) is a promising approach which exploits the huge available internal memory bandwidth. High capacity, wide row size, and maturity of DRAM technology, make DRAM an alluring structure for PIM. However, dense layout, high process variation, and noise vulnerability of DRAMs make it very challenging to apply PIM for DRAMs in practice. This work proposes a PIM structure which eliminates these DRAM limitations, exploiting a precharge-free DRAM (PF-DRAM) structure. The proposed PIM structure, called PIPF-DRAM, performs parallel bitwise operations only by modifying control signal...

Circuit-aging modeling based on dynamic MOSFET degradation and its verification

, Article International Conference on Simulation of Semiconductor Processes and Devices, SISPAD, 7 September 2017 through 9 September 2017 ; Volume 2017-September , 2017 , Pages 97-100 ; 9784863486102 (ISBN) Rohbani, N ; Miyamoto, H ; Kikuchihara, H ; Navarro, D ; Maiti, T. K ; Ma, C ; Miura Mattausch, M ; Miremadi, S. G ; Mattausch, H. J ; Sharif University of Technology

2017

Abstract

The reported investigation aims at developing a compact model for circuit-aging simulation. The model considers dynamic trap-density increase during circuit operation in a consistent way. The model has been applied to an SRAM cell, where it is believed that the NBTI effect dominates. Our simulation verifies that the hot-carrier effect has a compensating influence on the NBTI aging of SRAM cells. © 2017 The Japan Society of Applied Physics

Recent activities in science and technology and the progress of women in physics in the last three years in Iran

, Article AIP Conference Proceedings, Stellenbosch ; Volume 1517 , 2013 , Pages 108-109 ; 0094243X (ISSN); 9780735411388 (ISBN) Izadi, D ; Azad, M. T ; Mahmoudi, N ; Izadipanah, N ; Eshghi, N ; Sharif University of Technology

2013

Abstract

For the 4th IUPAP International Conference of Women in Physics, we report on activities in science and engineering in Iran, and conditions for women in physics, in the three years since the 3rd IUPAP International Conference of Women in Physics was held in 2008. Iran has made prominent advancements and astonishing progress in laser technology, biotechnology, nanotechnology, genetics, computer software and hardware, and robotics. Iranian scientists have been very productive in several experimental fields, such as pharmaceutical, organic, and polymer chemistry. Conditions for women in physics have improved greatly in recent years. A project to improve the environment for learning physics, and...

Lead-free MAGeI3 as a suitable alternative for MAPbI3 in nanostructured perovskite solar cells: a simulation study

, Article Environmental Science and Pollution Research ; Volume 30, Issue 19 , 2023 , Pages 57032-57040 ; 09441344 (ISSN) Mehrabian, M ; Akhavan, O ; Rabiee, N ; Afshar, E. N ; Zare, E. N ; Sharif University of Technology

Springer Science and Business Media Deutschland GmbH 2023

Abstract

The lead is a heavy metal with hazardous impacts on environment and human life. Lead-free perovskite solar cells have attracted much attention in recent years, due to eco-friendly characteristics. Meanwhile, Pb-containing cells showed the highest efficiencies among the various types of cells. Hence, designing novel Pb-free solar cells with comparable or better performance than the Pb-containing ones is highly required. In this work, a lead-free methyl-ammonium-germanium-iodide (MAGeI3)-based perovskite solar cell with ITO/TiO2/MAGeI3/Spiro-OMeTAD/Ag multilayer nanostructure has been proposed and its main characteristics including open-circuit voltage (VOC) and power conversion efficiency (η)...