Sharif Digital Repository

A low power 4-bit flash ADC is proposed. A new power reduction technique is employed which deactivates the unused blocks in the converter structure in order to reduce the power consumption. A new method for built-in threshold voltage generation together with a new offset calibration method is used to further reduce the power consumption in the converter. Monte-Carlo simulation shows that after calibration both the INL and the DNL are lower than 0.35 LSB. The converter achieves 3.5 effective number of bits (ENOB) at 1.2 GS/s sampling rate after the offset calibration is performed. It consumes 10 mW from a 1.8 V supply, yielding a FoM of 560 fJ/conversion.step in a 0.18 μm standard CMOS... 

A low power 4-bit, 1.6 GS/s flash ADC is presented. A new power reduction technique which masks the unused blocks in a semi-pipeline chain of latches and encoders is introduced. The proposed circuit determines the unused blocks based on a pre-sensing of the signal. Moreover, a reference voltage generator with very low static power dissipation is used. Novel techniques to reduce the sensitivity to dynamic noise are proposed to suppress the noise effects on the reference generator. The proposed circuit reduces the power consumption by 20 percent compared to the conventional structure when a Nyquist rate OFDM signal is applied. The INL and DNL of the converter are smaller than 0.3 LSB after... 

This work presents a behavioral model for non-ideal effects in a novel Hybrid time-interleaved digital to analog converter (TIDAC). In Hybrid DACs, both ΔΣ and Nyquist structures are used. In this work, in the Nyquist path, the 2-time-interleaving technique is used and in the ΔΣ path, a new structure is proposed to reduce the critical path in the TI delta-sigma modulator (DSM). In conventional TIDSM, adding each channel to the structure leads to increasing the critical path as one full-adder. This, in turn, decreases the speed of modulator since a single feedback loop is utilized to compute the running sum of the input signals. In this work, a new type of poly-phase decomposition is... 

A low-power fully linear integrated CMOS LC-based Digitally Controlled Oscillator is presented. The DCO operates in 5.2 GHz to 5.8 GHz range for using in IEEE 802.11a wireless applications. The system has been designed using 65 nm CMOS technology and 1.2 V supply voltage. By applying a proposed filter in DCO architecture −133.41 dBc/Hz phase noise at 1 MHz offset frequency from the fundamental carrier is achieved. The code generator and digital to analog converter designed to provide the high precision voltage required for fine-tuning. The output frequency swept through 10 control bits with 100 KHz resolution. The measured RMS jitter (∑ [1 KHz – 2 GHz]) from 5.8 GHz carrier is 1.65 fs. The... 

Due to wireless communication’s rapid growth, the need for low power integrated transceivers is increasing. The receiver power is a major limiting factor, and the radio frequency (RF) front-end is often its significant power consuming part. Therefore, system-level design in which the overall specifications are distributed among RF front-end building blocks such that the minimum total power is consumed is crucial. A complete system-level design method for a low power RF front-end is presented in this paper. For this purpose, the performance of each block is modeled by its current and overdrive voltage. An analytical associated with a search-based optimization technique is employed to derive... 

The application of time-interleaved structure leads to new amplitude and time errors while reducing many static and dynamic errors. In this case, both amplitude and time error are decreased by circuit structures integrated into a 7-bit DAC. In the present study, a new structure was proposed based on the randomization of two-interleaved paths in order to reduce the amplitude error, which can be extended to the N-channels-interleaved. In order to reduce the cycle-duty-error, a self-correction structure based on calculating the amplitude of the error before and measuring the time of this error along with the passage of the main signal through the output multiplexer is provided. The advantage of... 

A Digital Delta Sigma Modulator (DDSM) is a Finite State Machine (FSM); it is implemented using finite precision arithmetic units and the number of available states is finite. The DDSM always produces a periodic output signal when the input is constant. This paper proposes a novel method of applying periodic dither to a DDSM in order to obtain minimized spurious tones. The effects of adding the pseudorandom dither signal in different stages within the proposed Multi-Stage noise Shaping (MASH) modulator are expressed in the equations, and the results are compared. We present results regarding the periodicity of the quantization noise produced by a MASH modulator with a constant input and a...