Sharif Digital Repository

A method to design a tunable low noise amplifier (LNA) for multiband receivers is proposed. This paper also presents a single-ended to differential conversion (S2DC) topology which improves the LNA linearity without degrading its noise performance. Combining input tuning with S2DC in a single stage reduces power consumption of the LNA and decreases effects of supply noise. An LNA has been designed based on the proposed method for 2.3-4.8 GHz in a 0.18 μm CMOS technology. Simulations show an IIP3 of -3.2 dBm, a less than 3.7 dB noise figure (NF), a voltage gain of 24 dB in the whole frequency range. The LNA draws 13.1 mW from a 1.8 V supply. The results indicate that the proposed tuning... 

On-chip accurate clock references are one of the essential building blocks in fully integrated Systems-On-Chips (SOC). In this paper, a low phase noise, temperature and supply voltage independent clock reference is presented. It provides the reference frequency for a biomedical implantable system. The simulated phase noise at 100 KHz offset from 2MHz carrier is 113dBc/Hz. Simulations show the frequency remains within 0.34% of the nominal oscillation frequency in the operating voltage range of 1.7 - 1.9 V without any calibration and its change in the temperature range of 20-to100C is 0.5%. The circuit consumes 77W and is designed in a 0.18m technology with 1.8V supply voltage  

A systematic procedure of simulating charge pump based delay locked loops (DLLs) represents in this paper. The presented procedure is based on the systematic modeling of the DLL components in Matlab Simulink simulator. The system has been designed for 1Hz input clock signal that by changing the whole system scale, it can be used for every other input frequencies. The simulation results in Matlab and design considerations for DLL based frequency multiplier are presented  

A 1-V CMOS current steering digital to analog converter with enhanced static and dynamic linearity is presented. The 14-bit static linearity is achieved by a background analog self calibration technique which is suitable for low voltage applications and does not require error measurement and correction circuits. To improve dynamic linearity at high frequencies a track/attenuate output stage is used at the DAC output. Integral and differential nonlinearities of the proposed DAC corresponding to 14-bit specification are less than 0.35 and 0.25 LSB respectively. The DAC is functional up to 400MS/s with SFDR better than 71 dB in the Nyquist band. The circuit has been designed and simulated in a... 

An inductorless low noise amplifier (LNA) with active balun for digital TV (DTV) applications is presented. The LNA exploits a noise cancellation technique which allows for simultaneous wide-band impedance matching and low noise design. The matching and amplifier stages in the LNA topology perform single-ended to differential signal conversion with balanced output. The second and third-order nonlinearity of the individual amplifiers as well as the distortion caused by the interaction between the stages are suppressed to achieve high IIP2 and IIP3. A method for intrinsic cancellation of the second-order interaction is employed to reduce the dependence of the IIP3 on the frequency spacing... 

This paper presents a new architecture for a DLL based frequency synthesizer for wireless transceivers. Owing to its DLL based nature, the synthesizer generates the target frequencies with minimum phase noise. The proposed architecture takes the advantage of a combination of a frequency divider and an edge combiner to create the desired frequencies. As an example, the synthesizer is adopted to create the channel frequencies of French DVB-H/T standard. The circuit level design guidelines and power consumption trade-offs are presented. It was shown that for the mentioned standard a mere 6 stage delay line is sufficient. Simulation results confirm the analytical predictions  

A technique to reduce close-in phase noise in CMOS LC voltage controlled oscillators is proposed. In CMOS differential LC oscillators, the up-conversion of flicker noise mainly determines the close-in phase noise. The flicker noise of the bias current is a major component contributing to the overall low frequency noise. In this paper, a switched biasing technique to suppress the flicker noise of the bias circuit is presented. A 1.8v 2.4GHz differential LC VCO is designed in a 0.18u CMOS technology using this technique. With the proposed switching technique, the close in phase noise is improved as much as 15dB at 500 kHz offset. The simulated phase noise at the offsets of 500 kHz and 1 MHz is... 

Accelerated bridge construction is recognized as an important method for bridge owners to accelerate the delivery of highway bridge projects. While the potential advantages of accelerated bridge construction are recognized, it is difficult for transportation specialists to quantify the risks and benefits of using accelerated bridge construction compared with conventional construction for specific bridge replacement or rehabilitation projects. A tool set, based on the analytic hierarchy process, is prepared for transportation specialists and decision makers to determine whether accelerated bridge construction is more effective than traditional construction for a given bridge replacement or... 

The American Association of State Highway and Transportation Officials (AASHTO) and Federal Highway Administration (FHWA) encourage the use of various Accelerated Bridge Construction (ABC) strategies, which can help reduce onsite construction time, minimize traffic and environmental impacts, improve work zone safety, and deliver longer lasting and more durable bridges. ABC approaches include the application of technical innovations and management techniques. The decision to use ABC must be made on a project-by-project basis as each bridge location is unique, and factors constraining each project are different. Toward this end, FHWA developed a qualitative decision making framework called... 

A 1-V CMOS current steering digital to analog converter with enhanced static and dynamic linearity is presented. The 14-bit static linearity is achieved by a novel background analog self calibration technique which is suitable for low voltage applications and does not require error measurement and correction circuits. To improve dynamic linearity at high frequencies, a new low power track/attenuate output stage is used at the DAC output. Integral and differential nonlinearities of the proposed DAC corresponding, to 14-bit specification are less than 0.35LSB and 0.25LSB, respectively. The DAC is functional up to 400MS/S with SFDR better than 71dB in the Nyquist band. The circuit has been... 

In this paper, a new highly convergent, efficient, and fast response control technique entitled as fuzzy-Padé control method is introduced. It provides a simple methodology to exploit the heuristic knowledge in controlling a system. Fuzzy-Padé controllers originate from a unification of heuristic knowledge expressed as the rule base, and Padé approximants. In this method, fuzzy singleton rules are used to generate the rule base. Accordingly, unknown parameters in the Padé approximant are determined using these rules. The fuzzy-Padé controllers possess certain advantages over fuzzy controllers, and they can be applied in situations where fuzzy controllers previously failed. To demonstrate the... 

This paper represents a systematic procedure of simulating charge pump based delay locked loops (DLLs). The presented procedure is based on the systematic modelling of the DLL components in Matlab simulink simulator. The system has been designed for 1Hz input clock signal that by changing the whole system scale, it can be used for every other input frequencies. The simulation results in Matlab and design considerations for DLL based frequency multiplier are presented  

An efficient synthesis of highly substituted thiophenes was developed by means of sulfonylketenimines in a multi-step reaction including heterocumulene system containing sulfur and nitro-alkanes with acidic α-hydrogen. The speed and ease of conducting this four-component reaction under mild conditions and using available materials makes it an ideal method to synthesize high purity substituted thiophenes with sulfonamide moiety. All structures synthesized are confirmed by the instrumental analysis (EI-MS, IR and 1H /13C-NMR). © 2019, © 2019 Informa UK Limited, trading as Taylor & Francis Group  

In this paper we propose a novel structure of a discrete-time mixed-signal linear equalizer designed for analog front end of Gigabit Ethernet receivers. The circuit is an FIR filter which involves 6 taps based on a coefficient-rotating structure. Here, a simple structure is used for merging digital to analog conversion of the filter's coefficients and multipliers needed for 6 taps. This structure results in high speed and low power dissipation as well as less A/D converter complexity. Simulated in a 0.18 um CMOS technology, this equalizer operates at 125 MHz while dissipating 10 mw from a 1.8 V power supply. © 2006 IEEE  

This paper presents a new prediction model based on empirical mode decomposition, feature selection and hybrid forecast engine. The whole structure of proposed model is based on nonstationarity and non-convex nature of wind power signal. The hybrid forecast engine consists of three main stages as; empirical mode decomposition, an intelligent algorithm and three stage neural network. All parameters of proposed neural network will be optimized by intelligent algorithm. Effectiveness of the proposed model is tested with real-world hourly data of wind farms in Canada, Spain and Texas. In order to demonstrate the validity of the proposed model, it is compared with several other wind speed and... 

This paper presents a new prediction model based on empirical mode decomposition, feature selection and hybrid forecast engine. The whole structure of proposed model is based on nonstationarity and non-convex nature of wind power signal. The hybrid forecast engine consists of three main stages as; empirical mode decomposition, an intelligent algorithm and three stage neural network. All parameters of proposed neural network will be optimized by intelligent algorithm. Effectiveness of the proposed model is tested with real-world hourly data of wind farms in Canada, Spain and Texas. In order to demonstrate the validity of the proposed model, it is compared with several other wind speed and... 

Various methods are used in thermal power plants to adjust the superheated or reheated steam temperature to a pre-determined set point, including flue gas recirculation, using tilting burners and spray of water from discharge of feed water pump, etc. In this paper, an innovative method is presented to control the reheater temperature by tapping water from an interstage of the feed water pump to control reheater temperature at the Bisotoun Power Plant (a steam cycle based power plant in the western Iran). The spray water for the superheaters is secured from the discharge of feed water pump, but interstage water, instead of gas recirculation or using tilting burner, is used to control the... 

In this paper a new low-voltage two-stage class-AB line driver for ADSL applications is presented. The new proposed line-driver consists of only two stages with a new method to control the quiescent current of the output stage. The low-voltage full-CMOS high-linear line driver shows -77 dB THD for a load as low as 20 ohms. The line driver has variable gain, attenuating the input signal from 0dB to -14dB with 2dB steps. The peak to peak differential output swing is 4.2-V from a 2.5-V Supply voltage in a 0.25um standard CMOS technology