Sharif Digital Repository

One of the most important parameters of implanted chip in body is its ability to work for a long time without the need for battery change. Hence designing radio frequency transceivers used in these chips should be done with the lowest possible power consumption. Of course it should be noticed that for correct communication, standard specifications must be meeted. In this thesis, a receiver in medical implant communication service standard with the goal of minimal power consumption is designed. In circuit design different challenges such as low inductor quality factor, threshold voltage of transistors and usual trade-offs between receiver parameters are faced. Therefore, previous used... 

A key point in designing class-C oscillators is maximizing the Figure-of-Merit (FoM). For this purpose, changing the oscillator’s structure or adjusting its bias current may be used. Previous literatures mostly limit their efforts to the first case, leaving the issue of determining the proper bias current almost untouched. In this work, a new approach recruiting DC voltage of the common source node of the switching pair transistors as an indicator has been presented. Using theoretical analysis, it has been shown that maximizing this voltage will optimize the oscillator in term of the FoM. The proposed indicator has the advantages of not introducing any loading effect to the output node, and... 

The telecommunication manhole is a place that the cables of the telephone network are located on it. line Inside these manholes, there are equipment and cables for telephone. The number of these places is many, so protection and maintenance of the manholes have been problematic in case of theft of the cap, equipment inside them and flooding. Also, lack of inspection officers and the high cost of repairing and replacing parts inside them, has made it difficult for telecom companies to handle these problems. The only way to connect the manhole is a telephone line inside them. Also, there is no proper electrical power inside the manhole, so the design and implementation of a system that... 

Frequency synthesizers are one of the most critical building blocks of RF systems. Their task is to produce high-frequency precise and stable clock signals from a low-frequency source. The signal used in mixers to up-convert and down-convert desired signals in transceivers and the precise clock of analog to digital converters are made by frequency synthesizers. Designing frequency synthesizer, because of its lots of parameter and dependency of these parameters to each other, is a hard task which forces designers to propose new structures. In this thesis, an integer-N frequency synthesizer for Bluetooth application, with the goals of decreasing spurious tones power and settling time, is... 

The wideband code-division multiple access (WCDMA) system has been widely used for the third-generation wireless communication system. It uses Frequency division duplexing for two-way communication by a transceiver. Although a duplexer will significantly suppress the TX leakage signal (50dB-60dB), a residual attenuated signal still remains at the receiver input and act as a strong blocker which reduces the sensitivity of the receiver. For reducing the effect of the TX leakage on the RX performance, a band pass RF SAW filter is typically inserted between the LNA and the mixer to reject the TX leakage. However, this filter increases the system cost and size. This encouraged us to propose a novel... 

Transistors’ miniaturization and advent of short-channel effects causes searching for another devices with least adverse characteristics in short channels. Among all the considered devices, monolayer transistors attracted the attention. Although most of the papers in literature focused on the physical phenomenon of the device, circuit design of these transistors have been overlooked. Most of the papers related to monolayer transistors did not explain the design methodology of their circuits and they confined their work just to the report of the circuits constructed with 2D-based transistors. In order to take advantage of 2D materials in electronic circuits, simple modelling for... 

Efficient radio frequency (RF) power amplifiers (PAs) are critical in portable battery-operated wireless communication systems because they can dominate the power consumption. Linear amplifiers are enough linear but suffer from poor efficiency. On the other hand, switching power amplifier are efficient but are nonlinear and just amplify constant envelope signals. Two conventional methods for increasing transmitter efficiency and linearity are envelope elimination and restoration (EER) and envelope tracking (ET). In both methods, supply modulator controls RF power amplifier supply based on the signal envelope. Efficiency and bandwidth are critical factors in supply modulator. Thus hybrid... 

Various safety systems have been designed and developed in recent decades, but one of the most important issues is the improvement of safety of such systems and that is the goal of this research. In this thesis, while introducing different methods of designing an electronic system, we designed one of these safety systems: the Airbag system in accordance with ISO 26262 by considering standard requirements, prediction of potential hazards of the system, and its safe design at the system level. The designed system is capable of detecting the car crash in a precise and timely maner. The airbag will deploy within 45 milliseconds protecting the health and safety of occupants of the car and in... 

Phase shifters are commonly used in the implementation of phased-array antenna systems.The function of these systems is highly dependent on the performance of phase shifters. In addition, phase shifter circuits are used in some applications such as antenna test and regulation, power amplifier linearization, and QAM modulator implementation, to name but a handful. In this project, design of phase shifter blocks, as well as limitations of fabrication on silicon substrate, is studied and these blocks are designed for maximum bandwidth and minimum sensitivity based on fabrication characteristics and environmental conditions. Design of a 6-bit phase shifter based on vector-sum method is the... 

Ever increasing applications of embedded systems have motivated the designers to pay special attention to the design requirements of such systems. Among embedded applications, safety-critical systems have high reliability requirements as failures in such systems may endanger human life or result in catastrophic consequences. Embedded processors as the computation cores of embedded systems are very crucial from reliability point of view. This is because; a failure in the processor most probably leads to a system failure. One effective way to protect embedded processors against environmental faults is to use system level fault-tolerant techniques such as Master/Checker (M/C) or Triple Modular... 

In recent years, the use of embedded processors has grown increasingly in wide range of computer systems; so that most of manufactured CPUs are used in emebedded systems many of which are safty-critical systems such as medical devices, aircraft flight control, space systems, nuclear systems, etc. The incidence of failure in these systems can cause irreversible damages on human life, financial or environmental matters. Silicon process technology trends, such as reducing the threshold voltage, increasing the frequency and decreasing the size of transistors, not only caused increase in single-bit fault rate but also caused occurance of multi-bit faults. Due to importance ofcorrect operation of... 

Nowadays, one of the most important challenges in the design of digital circuits is their susceptibility to the strike of high energy particles which leads to the Single Event Transient (SET) and Multiple Event Transients (MET). In fact, technology scaling which results in lower supply voltage, higher operating frequency, and lower nodal capacitance, makes today’s digital circuits more susceptible not only to high energy particles but also to low energy particles. Moreover emerging deep sub-micron technologies and the integration of more cells in today’s chips have caused higher probability of MET occurrences. A lot of research has tried to reduce the soft error rate due to high energy... 

Wireless Sensor Networks (WSNs) are prone to faults due to battery depletion of nodes, where a node failure can disturb routing, as it plays a key role in transferring sensed data to the end users. A WSN may be partitioned into groups of nodes called clusters; for every cluster, there is a node, called Cluster Head (CH) that is responsible for collecting and transferring data from all nodes in that cluster. This means that the CH is a single point of failure; i.e., once a CH fails, the whole cluster will fail, which leads to inability of its members for transferring data outside the cluster. This thesis presents a Fault-Tolerant and Energy-Aware algorithm (FTEA), which prolongs the lifetime... 

Vulnerability of SRAM-based FPGAs to soft errors signals the importance of applying fault-tolerant methods in FPGAs used in safety-critical applications. Previous methods to protect SRAM-based FPGAs impose significant area and power overheads. Additionally, they suffer from susceptibility of configuration bits to Single Event-Multiple Upsets (SEMU). This thesis presents a Highly Available Fault-Tolerant Architecture (HAFTA) to protect SRAM-based FPGA designs against SEMUs in both configuration and user bits. In HAFTA, the entire design is duplicated and the main and replica flip-flops are compared at each clock cycle to detect any possible mismatch. To save the latest correct state of the... 

The increasing size of valuable data emphasizes the importance of applying reliability in storage systems. One way to protect storage system failures is using erasure codes. The advantages of using erasure codes are their low overheads and high reliability. Soft errors caused by high-energetic particles do not only corrupt data in the SSD-based storage systems, but also in the erasure codes. In this regards, it is important to protect erasure code implementations against soft errors. This thesis proposes a fault-tolerant implementation of erasure codes. The proposed method is based on the structure of each erasure code. This method is analytically evaluated on four erasure codes, i.e.... 

With continuous device down-scaling and increase in transistor counts on a chip, complementary metal-oxide-semiconductor (CMOS) technology has become extremely sensitive to soft errors. Soft errors are transient errors caused by energetic particles such as neutrons and alpha particles. An essential step to design a soft error tolerant digital system with minimal performance and power overheads is Soft Error Rate (SER) estimation of system components. Until recently, Single Event Upsets (SEUs) in latches and Filp-Flops (FFs) and Single Event Transients (SETs) in combinational logic parts of digital circuits were regarded as the main effects of particle strikes. However, with the emerging... 

Increasing complexity of embedded systems and the need for more computation powerhave directed designers toward using of multiprocessors. SRAM-based FPGAs are suitable platforms for implementation of multiprocessors due to thier low cost, fast time-to-market and re-configurability. FPGA-based multiprocessors are known as soft multiprocessors. The large area of SRAM-based FPGAs is occupied by configuration bits. Configuration bits are vulnerable to high energy particles that can lead to soft errors. In this regards, it is of decisive importance to protect soft multiprocessors against soft errors. This thesis proposes a fault-tolerant method for soft multiprocessors that can detect and... 

The use of flash-based Solid State Disks (SSDs) has been increased in the past decades because of their high performance and low power consumption. As SSDs have no moving mechanical parts, they are more reliable than HDDs. SSDs have specific errors, such as read, program, and erase disturbs, data retention, and endurance. It is so common in storage systems to apply an array of disks called Redundant Array of Independent Disks (RAID) together for the aim of reliability and performance. Erasure codes are one of the main methods applied in storage systems for the aim of reliability. Erasure codes increase the reliability of storage systems by protecting them against disk failures and sector... 

One of the major challenges that threat the reliability of NoC-based systems is Crosstalk fault. Some effects of crosstalk fault such as Rising/falling delays and rising/falling speed-ups lead to the variations in channel delay, incorrect data transmission, and extra power consumption in NoC communication channels. Crosstalk fault is data dependent and the intensity of this fault seriously depends on the transition patterns appearing on the wire during the data traversal between processing elements. Most of mechanisms tackling crosstalk fault that are discussed in literature are based on 3-wire delay model. In 3-wire delay model, one wire is considered as victim wire and classification of...