Sharif Digital Repository

Heterogeneity is one of the challenges in the current NoC (Network-on-Chip) domain which oblige designers to consider less regular topologies to provide the best cost-performance trade-off while minimizing resource and power consumption and providing the maximum flexibility. Irregular mesh is a topology which combines the benefits of regularity and advantage of irregularity. Another important issue in any NoC is the selection of routing algorithm which provides the best performance. Routing algorithms especially those coupled with wormhole switching should deal with deadlock occurrences. Deadlock detection and recovery-based routing schemes for this type of switching gained attraction since... 

The increasing complexity of integrated circuits drives the research of new on chip interconnection architectures. Network On Chip (NoCs) are a candidate architecture to be used in future systems, due to its increased performance, reusability and scalability. A NoC is a set of interconnected switches, with IP cores connected to these switches. Different routing algorithms have been proposed for NoCs such as XY deterministic algorithm, and WF (West First), NL (North Last) and NF (Negative First) as partially adaptive algorithms. OE (Odd Even) is not based on adding virtual channels to network topologies. Unlike previous methods, which rely on prohibiting certain turns in order to achieve... 

One of the most important factors in using wireless networks is to enable the nodes to move. Thus, it is crucial to a wireless network designer or analyst to investigate the effect of mobility of the nodes on the performance of mobile wireless networks. This problem is considered here in a systematic approach. The general approach proposed is the intermediate performance modeling. After introducing the theoretical framework, link statistics is used as intermediate performance measures and the rest of the work is conducted in two lines. We first show that such measures can be obtained analytically or by experiments and then use them to obtain analytical results about different protocols. For... 

In this project we present a method to support execution of multiple applications on an NoC simultaneously. To this end we are going to use resource sharing methods, especially Spacial Division Multiplexing (SDM). In this work we first present a mapping algorithm to map the nodes of a compound graph (a graph that is composed of all the task graphs that are supposed to work simultaneously) in to mesh nodes. We also present an architecture to support SDM. After that we present a routing and resource allocation algorithm to find a circuit for each communication flow in the task graph. Our results show that the proposed mapping algorithm reduces the average packet latency compared to NMAP... 

Network-on-Chip (NoC) is a promising on-chip communication paradigm which targets the scalability and predictability problems of the traditional on-chip mechanisms. However, it has been shown that, in future technologies (especially 22 nm technology), the power consumption of the current NoCs is about 10 times higher than the power budget can be devoted to them. Application-specific optimization is one of the most effective approaches to bridge the exiting gap between the current and the ideal NoC power consumptions. However, almost all existing application-specific customization methods try to customize NoCs for... 

Studying data flows in conventional applications of Multi-Processor System-on-Chips (MPSoCs) denotes that most of these flows are the ones that transfer huge volume of data in inter-core communications. Previous works try to present architecture for interconnection network which some paths with low power and latency are reserved (statically or dynamically). However all of the presented methods are based on subnetworks or mechanism of transferring control messages (to establish a path and tear it down after transmission of data). Optical connections with low cost, low power and high bandwidth are good candidates to reduce power consumption of Network-on-Chips (NoCs). Therefore, using optical... 

Peer-to-Peer network has given a great deal of notice in last few years, and a large number of scientific conferences and publications have focused on this issue. Development of P2P networks has been rapidly done as a large fraction of the internet traffic is generated by P2P application in different fields such as content-distribution (iBBC), privacy protection (Tor), file sharing (bit-torrent), real- time communication (Skype), web-based search (YaCy), and so forth. So, the tremendous growth of P2P network escalates the importance of researching in this field. In this thesis, we tried to study different models over P2P networks and use hybrid approach in our design. In general [22],... 

From the programmer’s point of view, main memory allocation to a program is contigious, however this is non-contigious and the program is scattered in physical memory here and there. Assuming main memory partitioned into regions, each program accesses in its life time different regions which are not necessariliy close and occupy different percentages of the cache capacity. Considering what the replacement policy is chosen, the cache would be partitioned differently among regions, e.g., the commonly used LRU policy partitions the cache among regions on a demand basis, giving the more cache resource to regions whose miss ratio is higher, which is not necessarily optimal. In this thesis, we... 

Project in brief: reconfiguring the network according to application which has been run on the network is one of the ways to improve using resources in the network-on-chip. There is a hierarchical cluster based NOC. In this network, nodes are going to partition into clusters. Every cluster’s node can have its own configuration and the configuration of inside of each cluster is unchangeable however the relationship between clusters is configurable. This ability is made by some switches which are located between clusters and they can change the way that clusters are related. The number of nodes which is inside the cluster are cluster size and the number of switches between two adjacent... 

Modern pipelined processors use a memory array named Branch Target Buffer (BTB) to reduce the performance penalty due to conditional braches by predicting path of the branch and keeping useful history-based information for future accesses. Today BTB is a fixed size and small memory array located near the processor. By the way, BTB, in the best case, should be large enough to accommodate all conditional branches throughout the running program. Moreover, small size BTB presents much fast access and is practical on-chip storage for a system with limited power budget.
Considering role in the memory hierarchy, on the other hand, the system performance is highly correlated to the L1 data cache... 

Switching as one of important characteristics of on-chip network affects on power consumption and performance. In general there are two switching methods as circuit-switching and packet-switching. Hybrid switching includes both switching to have both resource utilization and scalability of packet switching and low power consumption and improved latency of circuit switching. Also topology is another network attribute that greatly affects the power, performance, cost, and design time/effort of NoCs. In this thesis, we propose a novel NoC architecture which holds both fixed connections between adjacent nodes and long connections virtually connecting non-adjacent nodes. Our proposed NoC... 

General-purpose Chip Multiprocessors (CMPs) are used to run a wide range of applications. Task-to-network mapping is one of the best NoC optimization methods which highly affects the NoC power and performance metrics. However, this kind of optimization can be applied
only when the input application and its traffic pattern is known in advance and is described by a communication task-graph. However, for some applications, such as multimedia and network applications, the communication task graph is not known in advance. Hence, we cannot achieve an optimum task mapping by using the existing mapping algorithms. In this thesis, we aim to address this problem by proposing a distributed run-time... 

On-chip communication infrastructure in chip multiprocessors with large number of processing cores has to be scalable, consumes low power, and provides high bandwidth for hundrededs or even thousands of processing cores. In this project, to this end, the applicability of wireless network technology for on-chip communications in systems with hundreds or thousands of processing elements is investigated. We have combined wired networks (for communication between elements that are close) and wireless networks (for transmition of high volume data flows between cores that are far from each other); so different data flows achive the required bandwidth and point to point delay is reduced. Also, a... 

As feature size of transistors in deep sub-micron technologies decreases, serious problems emerge in term of scalability, power consumption and memory access latency. A new approach to mitigate these drawbacks is to use non-volatile memory as probable alternative. Among different alternatives, Phase Change Memories (PCMs) are more likely to be used in place of conventional memories. Since fabricating PCM with 2D fashion design is a high-cost process, 3D integration is known as a good candidate solution according to its fabrication process flexibility. In 3D ICs, the increase in power density leads to elevated on-chip temperature that results in large reduction of read and write power... 

In this paper, we propose a run-time strategy for managing writes onto last level cache in chip multiprocessors where STT-RAM memory is used as baseline technology. To this end, we assume that each cache set is decomposed into limited SRAM lines and large number of STT-RAM lines. SRAM lines are target of frequently-written data and rarely-written or read-only ones are pushed into STT-RAM. As a novel contribution, a low-overhead, fully-hardware technique is utilized to detect write-intensive data blocks of working set and place them into SRAM lines while the remaining data blocks are candidates to be remapped onto STT-RAM blocks during system operation. Therefore, the achieved cache... 

Delay Tolerant Networks are a variation of Mobile Ad Hoc Networks, in which low density of nodes in the network area results in global disconnectivity among the nodes. In these networks, communication of data throughout the networks takes place by the means of mobility; nodes store data packets and carry them around the network and forward them to other nodes they encounter along the way. In these situations, a proper selection of data to be exchanged between nodes has a great impact on the quality of data distribution in the whole networks. There is a common assumption among most of the techniques presented in category of Delay Tolerant Networks. They assume the probability of more than two... 

Advance in VLSI integration level has realized multi-core system-on-chip. For inter-IP communication on-chip network is proposed as a substitute for simple interconnects such as bus fabrics and expensive point-to-point links. Although onchip networks have some superiorities over simple interconnects, but they need more of real estate resource. Although buses are not scalable, they are still popular for their simple communication mechanism. There are so many proposed mechanisms to make buses more scalable and more popular. Most of them try to change bus structure by segmenting and using reconfigurable methods. In this thesis, we explore buses delay by considering the number of component in a... 

Real-time (RT) communication support is a critical requirement for many complex embedded applications which are currently targeted to Network-on-chip (NoC) platforms. Average Delay and Average Bandwidth are historically the popular metrics used to evaluate the performance of an on-chip network. For RT communication, guaranteeing Minimum Delay and Maximum Bandwidth (performance bounds) which are known as the metrics for Quality-of-Service (QoS) have been at great importance during recent years. Networks-on-chip are classified to Best-Effort (BE) and Guaranteed-Service (GS) networks. Packets are processed without any precedence in BE networks, while there are special hardware and controlling... 

A city is a complex system which consists of many interactive sub-systems. It is affected by diverse factors including governmental land policies, population growth, market behavior and transportation infrastructure. Traffic congestion is one of the most critical challenges of transport infrastructure which became everyday occurrence in the last decades. The traffic planners and traffic engineers have faced real obstacles due to the growth of motorization and the resulted external consequences. Furthermore the capacity of the traffic networks saturates during rush hours. Generally, network transport performance can be improved in two ways, optimizing network structure (Hard Strategy) or... 

As a promising replacement for the conventional high-latency and low-throughput HDDs, NAND Flash-based solid state drives have been increasingly used in data center and cloud applications as well as high-end enterprise servers. However, capacity scaling is a controversial challenge of the SSD manufacturers to keep pace with the competitors in the storage market. To date, SSD designs have been largely based on multi-channel bus architecture that confronts serious scalability problems in high-end enterprise SSDs with dozens of Flash memory chips and a gigabyte host interface. This forces the community to rapidly change the bus-based inter-Flash standards to respond to ever increasing...