Sharif Digital Repository

This thesis revises the conventional design of oscillators and presents new methods for shaping and improving the phase noise curve of the oscillators. These methods are based on the position of the zeros and poles of transfer functions in the S-plane and choosing their orders also. This thesis shows that the position of the zeroes and poles of the transfer functions can affect the phase noise performance of the oscillators. The basic idea is maximizing the slope of the phase of the transfer functions. It is proved that the maximizing the slope of the phase can expectedly reduce the phase noise of the oscillators. Increasing the order of the transfer functions with the proper selection of... 

We present a novel and simple method to calculate each Fourier series coefficient of ISFs in LC oscillators, analytically. This new approach explains the relationship between Fourier series coefficient of ISF and oscillator topology and parameters. This technique helps designers to obtain the great insight of how to decrease the output noise in oscillators. This method also can be used to derive the waveform of ISFs in time domain.Based on the features of our new technique and by presenting a general method to change the stationary noises to Cyclo-stationary ones, we suggest a step by step design guide which elucidates new ideas for designers to manipulate the oscillator parameters and... 

In this thesis, we intend to explore the application of active inductors in high-performance radio receivers. The proposed active inductor uses a feed-forward path to improve the noise performance. This is done without sacrificing the quality factor and the power consumption. The proposed active inductor is designed and implemented in a standard 0.18μm CMOS technology. The measurement results show an almost three fold improvement in the noise performance, comparing to the typical existing structures. The resonance frequency of the inductor can be tuned from 1.8 GHz to 5.5 GHz, while the quality factor can be adjusted up to 30. The total current consumption of the active inductor is 4.8... 

In this thesis, at first, we study the active inductors have been reported in the literature. Then by choosing one of them and investigating its advantages and disadvantages, we changed the structure in a way to solve its problems. On the way by using this active inductor and a negative capacitor, we designed an oscillator in 1.5 GHz frequency that has -106 dBc/Hz phase noise at 1MHz offset and its FOM value is 160 dBc. Also this oscillator is capable of frequency tunability of oscillation from 500 MHz to 2.2 GHz. In this spectrum the phase noise is changing between -100 dBc/Hz and -110 dBc/Hz. In the second part, in the aim of improvement of phase noise of oscillator structures based on... 

A New method is proposed to find a mother wavelet for the best localization of acoustic emission (AE) signals generated by leakage in a pipe. At the first step, knowing stochastic nature of acoustic emission signals, a leakage signal in time domain was trapped by monitoring the Short Time Fourier transform (STFT) of AE signal over a relatively long time interval to find frequency traces of leakage AE signal. The trapped signal was used to find a mother wavelet for the best signal localization. Then a novel method for AE signal detection using tuned wavelet is discussed. For this purpose experiments were done in predefined situations to collect signals generated in water filled plastic pipe... 

A new analytic method for class E power amplifiers in the frequency domain is presented. Closed form and fairly simple equations in terms of the circuit components for the output power at the carrier frequency and its harmonics as well as the power efficiency with its sensitivity to the load resistance and other circuit components are derived. This provides the facility to directly calculate the circuit components for the desired operation. Using the proposed model, equations to satisfy maximum power efficiency are derived. Also, a design guide based on a novel scaling method to facilitate the design procedures for the given constraints and conditions are presented. In the next step, a... 

A new method for power amplification is proposed. By studying the N-path filter structure, the N-path Structure is employed for power amplifier design. The main feature of this method is that the power amplifier designed upon this structure can amplify the input signal in a multi-standard fashion. In addition, N-path structure eliminates the matching network at the output of power amplifier which usually is a complex circuit implemented off-chip. At the first step, mathematical relations are employed in order to find the appropriate structure for the power amplifier and efficiency optimization is done by means of new mathematical relations. In the next step, required blocks are designed for... 

In this Thesis, first, UHF RFID Class1 Generation 2 was studied accurately and Required Signaling, Timing and Circuit Parameters for Design Readers in this Band, was Extracted from Standard. an important algorithm for Tags inventory, that Protocol leaves the way of implementation to designer, was introduced and simulated. Also a effective method was presented that detect bit streams received by readers in low SNR. Some parts of Baseband Signal conditioning circuits, including filter and variable gain amplifier, wad designed in 0.18 um CMOS Technology. In Second part, communication protocol between server and readers was introduced with some Scenarios that make communication easier and make... 

In this research, the design of a broadband multi-phase frequency synthesizer, applicable for the multi-path structure in the 5G NR1 transmitter, is investigated. This standard presents new challenges for synthesizer design; The synthesizer in such a system must cover a wide frequency range. On the other hand, since this standard employs Orthogonal Frequency Division Multiplexing, it must meet the stringent requirement of integrated phase noise over multiple decades of frequency. The synthesizer employs the phase-locked loop architecture. The frequency division method has been used to construct eight symmetrical phases. The designed synthesizer can generate a frequency range of 600 MHz to 5... 

Degradation of signal to noise ratio (SNR) in today's low voltage circuits has been a challenging problem for analogue circuit designing. This problem is produced due to supply voltage reduction and noise level consistency in today's analogue circuits. Great efforts have been done in literatures for noise reduction in some analogue circuits, like low noise amplifiers, but there is no general method for noise reduction in active filters and introduction of a general method for noise reduction in active filters which are in vast usage in all analogue circuits, has always been demanded by circuit designers. In this project, a general method for noise reduction in active RC filters is introduced... 

Radio-Frequency Identification (RFID) in many applications, namely supply chain management; access management; tracking commodity, people, and animals; and storage of medical information, to name but a few, be remembered as the most effective method of gathering information. Accordingly, accurate modeling and optimizing of this technology with attention to its daily development in varied applications, has a significant role. In this regard, some issues – that is – reader location, the number of tags that are controlled by a reader, and data communications of readers with central server, to name but a handful, are challenging and there are attemps to optimize the network in terms of cost,... 

A 1.8-v 1.8-GHz fully integrated CMOS fractional-N frequency synthesizer is designed and tested for UHF RFID readers. The synthesizer employs a dual-loop architecture to realize a monolithic design with more optimal trade-off among phase noise, channel spacing, reference frequency and settling time compared to the conventional integer-N phase-locked-loop architecture. Due to the large self-interference and the backscatter scheme of the passive tags, reader synthesizer’s phase noise requirement is stringent to minimize the sensitivity degradation of the reader RX. A 1.8-GHz complementary VCO with noise filter has been used to achieve these tough specifications. Also, since a large KVCO can... 

There is a strong drive toward handheld communication devices with building blocks that are fully integrated in standard CMOS technologies. Although there are obvious cost, size, and repeatability advantages, it is particularly challenging to implement fully integrated power amplifiers with no external matching in standard CMOS under the large supply variations and harsh load mismatches present in handheld devices. This Project deals with the front-end of an Integrated RFID Reader for the UHF band. The bottleneck of the design is the design of a fully on-chip Power Amplifier. In this thesis, a new method is introduced to increase transistors breakdown voltage in a class E power amplifier.... 

Gain bandwidth products of Operational Amplifiers are dependent to power consumption. In this thesis we introduce negative capacitance circuit as a candidate to improve GBWs of OPAMPs in constant power, or achieve the requested GBW in lower power consumption. First we characterize negative capacitance circuit and introduce a model for that. Then we see how pole-zero placement will change, when we add negative capacitance circuit to a circuit node. As an application we use this circuit in Folded Cascode and Current mirror OPAMPs and give design guideline for this topologies. A three stages and a one stage OPAMP is designed in 0.18um CMOS, for the application of negative capacitance... 

The use of Radio Frequency Identification is increasing rapidly. The reason is the capability to transfer data wirelessly without line-of-sight necessity, high data rate and long read range. The main advantage of barcode is its lower cost which has ensured its existence for many years. The applications and materials that are identified by RFID increase as the price of RFID tags decrease. This Project deals with the transmitter of an Integrated RFID Reader for the UHF band. The bottleneck of the design is to integrate a high power PA with the noise sensitive blocks such as synthesizer. A layout design guide along with circuit considerations is presented to alleviate the problem of this... 

We present a model for noise in Ring Oscillator in order to improve their phase noise. Each Ring Oscillator consists of some nonlinear blocks. We study effect of these blocks on phase noise. In this study, noise behavior of each block is analyzed and a design guide for improvement of noise characteristic is presented.
It is essential for phase noise improvement to obtain insight about operation mechanism of oscillator. A comprehensive model is presented to get this insight. In this model, we show how a noise current produces phase noise also, a formula for phase noise is derived.
In second step, phase noise of Ring oscillator is improved by using the model. Active inductor is used in... 

Removing SAW filter from the input of a receiver makes the receiver extremely vulnerable to all sorts of blockers and interferers. It is shown in this thesis that due to existing large out-of-band blockers the linearity of the saw-less receiver has to be considerably higher than that of the conventional receivers with input SAW filter. These ever-present and unwanted signals that show up in the absence of the input SAW filter are divided into two groups of far and near out-of-band blockers and interferers. It is shown that removing these groups of unwanted signals require two distinct approaches, one for near and the other for the far out-of-band blockers. An inclusive solution to protect... 

An ultra-low-power wake-up receiver is proposed, which reduces the power consumption significantly under the two-mode duty-cycling and with negligible latency. Due to the use of an accurate LO and high Q BB filters, the receiver shows a perfect selectivity in the frequency domain, and appropriately fits practical dense environment applications. In this receiver, four start frame bits (SFB) are received at the low data rate of 1 kbps in the MO mode, and after entering the ID mode, a long wake-up pattern is received at the high data rate of 100 kbps. Therefore, the latency is limited to the SFBs and is roughly 4 msec. The proposed wake-up receiver is designed and fabricated in TSMC 180 nm... 

In this thesis, a wideband multi-standard digital transmitter based on the multi-path architecture has been designed in 65-nm CMOS process. Moreover, the effect of phase error of the clocks on the output specifications of this multi-path transmitter has been analyzed, and based on the derived theoretical equations, circuit-level solutions for the correction of these errors have been proposed. In addition to the circuit-level solutions for error correction of the clocks, a general setup for calibration of the multi-path transmitter has been presented. Also, several software-based algorithms for the calibration of the transmitter have been studied and their validity has been verified using...