Sharif Digital Repository

A 1.5-V single supply, second order continuous-time bandpass filter, on a 0.6μm standard CMOS process is designed. The THD of the transconductor for a 0.7Vpp input, is -50dB at 10-MHz. In the proposed transconductor structure, the whole circuit, apart from a dc level-shifter based on a voltage doubler, is biased by a single 1.5-V supply. Due to this structure, a high current voltage doubler is not required and the whole filter draws less than 70μm current from this doubler making an on-chip voltage doubler feasible. Also, a new linear common-mode detector with high-frequency response is designed to stabilize the output common-mode voltage. © 2002 IEEE  

A very low voltage transconductor for video frequency range applications and compatible with standard CMOS technology is described. In the proposed transconductor, except the DC level shifter circuit (DCLS), the whole transconductor uses the main supply voltage [which can be as low as 1.5 V in a standard 0.6 μm CMOS technology] while the DCLS uses a simple charge-pump circuit as its supply voltage and has a very low current consumption. In addition, proper common-mode sense and charge-pump circuits are developed for this low-voltage application. Meanwhile, some techniques to improve the frequency response, linearity, and noise performance of the proposed transconductor are described. In a... 

Modified two-phase latch and flip-flop are introduced to implement a linear phase-detector (LPD) for 1/N-rate clock recovery applications. This technique greatly simplifies the required circuitry of the LPD and makes it suitable for higher speed applications while consuming less power compared to the conventional techniques  

A structured design of Subscriber Line Interface System and Circuit will be described. A high level synthesis allows extracting overall system and circuit requirements to satisfy the desired specifications, standards, and a robust implementation. For this purpose, first the output driving stage will be analyzed and then, dc, ac, and longitudinal balance feedbacks will be considered. Then based on extracted system specifications, optimum circuit design of line-driver will be described. High-level design of line-driver as the most important circuit block which is optimized for stability, accuracy, area, and power dissipation will be elaborated. © 2005 Springer Science + Business Media, Inc  

A single 1.5 V supply, second order band-pass gm-C filter based on a low-voltage transconductor architecture in standard 0.6 um CMOS process is presented. A dc level shifter circuit (DCLS) is utilized at the input of the proposed transconductor to increase the dc level of the input signal. This makes the input transistors operate in the desired region and hence input voltage swing enhances. DCLS uses a simple voltage doubler as its supply while other parts of the circuit use the main 1.5 V supply. Proposed transconductor shows a THD of -60 dB for 1.4 Vpp,diff input signal with 1 MHz frequency. Also a proper common-mode detector circuit is developed for this low-voltage application. The... 

A structured design of Subscriber Line Interface System and Circuit will be described. A high level synthesis allows extracting overall system and circuit requirements to satisfy the desired specifications, standards, and a robust implementation. For this purpose, first the output driving stage will be analyzed and then, dc, ac, and longitudinal balance feedbacks will be considered. Then based on extracted system specifications, optimum circuit design of line-driver will be described. High-level design of line-driver as the most important circuit block optimized for stability, accuracy, area, and power dissipation will be elaborated  

This article explores the main tradeoffs in design of power and area efficient bandgap voltage reference (BGR) circuits. A structural design methodology for optimizing the silicon area and power dissipation of CMOS BGRs will be introduced. For this purpose, basic equations of the bandgap circuit have been adapted such that can simply be applied in the optimization process. To improve the reliability of the designed circuit, the effect of amplifier offset has been also included in the optimization process. It is also shown that the minimum achievable power consumption and area are highly depending on the fabrication process parameters especially sheet resistivity of the available resistors in... 

This paper studies the specifications of gated-oscillator-based clock and data recovery circuits (GO CDRs) designed for short haul optical data communication systems. Jitter tolerance (JTOL) and frequency tolerance (FTOL) are analyzed and modeled as two main design parameters for the proposed topology to explore the main tradeoffs in design of low-power GO CDRs. Based on this approach, a top-down design methodology is presented to implement a low-power CDR unit while the JTOL and FTOL requirements of the system are simultaneously satisfied. Using standard digital 0.18 μm CMOS technology, an 8-channel CDR system has been realized consuming 4.2 mW/Gb/s/channel and occupying a silicon area of... 

Carbon nanotubes are widely used in the design of nanosensors and actuators. Any defect in the manufactured nanotube plays an important role in the natural frequencies of these structures. In this paper, the effect of vacancy defects on the vibration of carbon nanotubes is investigated by using an atomistic modeling technique, called the molecular structural mechanics method. Vibration analysis is performed for armchair and zigzag nanotubes with cantilever boundary condition. The shift of the principal frequency of the nanotube with vacancy defect at different locations on the length is plotted. The results indicate that the frequency of the defective nanotube can be larger or smaller or... 

This paper introduces a low-jitter and wide tuning range delay-locked loop (DLL) -based fractional clock generator (CG) topology. The proposed fractional multiplying DLL (FMDLL) architecture overcomes some disadvantages of phase-locked loops (PLLs) such as jitter accumulation while maintaining the advantageous of a PLL as a multi-rate fractional frequency multiplier. Based on this topology, a CG with 1-2.5 GHz output frequency tuning range has been designed in a digital 0.18 um CMOS technology while the multiplication ratios are M+k/(2N C ) in which M, k, and N C are adjustable. To generate some finer ratios, k is changed periodically or randomly (by a digital delta-sigma modulator) between... 

In this paper, a new 1/4 rate clock linear phase detector (PD) structure for PLL-based clock and data recovery (CDR) circuits will be suggested. The proposed topology offers a more suitable PD for high speed applications compared to the conventional topologies. The effect of duty cycle variation on the operation of CDR has been also studied. Designed in a 0.18μm CMOS technology, the proposed PD consumes 16mA from a 1.8V voltage supply. © 2006 IEEE  

This article introduces a novel duty-cycle control circuit (DCC) preceding a delay-locked loop (DLL)-based clock frequency multiplier preventing the output duty-cycle over process, supply voltage and temperature (PVT) variations. However, the proposed DCC eliminates the effect of input duty-cycle variation and, hence, decreases the sensitivity to the input jitter and distortion. The circuit realisation in 0.5-μm CMOS technology shows that the duty-cycle variation at the output clock is less than 2.7%, while driving the digital section of a CODEC chip and also test pads. The analysis, confirmed by measurements, shows a stable and accurate response for the proposed clock generation unit (CGU).... 

A compact, low power, clock frequency doubler circuit with no external devices designed and manufactured in a 0.5um CMOS technology. Proposed circuit generates a 4.096MHz output clock frequency from a 2.048MHz input clock while an automatic duty cycle control circuit reduces the sensitivity of the duty cycle of output clock to the duty cycle of input signal or process and temperature we variations. For this purpose, an accurate delayed clock is generated. structure besides MOSFET capacitors offers a impact and low power circuit. The area of the circuit is 0.08mm2 while consumes 380uArms SV power supply and drives 15pF capacitor load. Measured output duty cycle shows a variance of 2.7% from... 

Micro-machining of face centered cubic (FCC) metallic materials is simulated via the theory of rate-dependent crystal plasticity. This approach accounts for slip systems and crystallographic orientations in its constitutive framework in order to accurately model the evolution of localized shear band formed during severe plastic deformation of crystalline materials. Through developing a user-defined subroutine in the ABAQUS/Explicit FE platform, the constitutive model is implemented and used to study the influence of workpiece crystallographic orientation on the cutting and thrust specific energies of the process. Due to the high rate of deformation, mechanical properties of texture can be... 

In this paper, the stability of delay differential equations (DDEs), describing self-excited vibrations in a micro-milling process, is investigated based on semi-discretization (SD) method. Due to the stubby geometry of micro-tools, the shear deformation and rotary inertia effects are considered for modeling the structure. The extended Hamilton's principle is used to derive a detailed dynamical model of the spinning micro-tool with the support of misalignment in which the gyroscopic effects cause coupling of equations. Considering the actual geometry of the micro-end mill, exact dynamic stiffness (DS) formulations are developed to investigate the tool's free vibration characteristics. The... 

In this paper, chatter instability of micro end mill tools is studied by taking into account the process damping effect. The actual geometry of the micro tool including shank, taper part and fluted section is considered in the analysis. Timoshenko beam theory is utilized to consider the shear deformation and rotary inertia effects due to short and thick beam-type structures of each parts of the micro tool. The extended Hamilton's Principle is used to formulate a detailed dynamical model of the rotating micro end mill. The governing equations are solved by assumed mode model expansion. An exact dynamic stiffness method is developed to investigate modal characteristics of the tool including...