Sharif Digital Repository

Monomer grafting, a unique technique for polysaccharide modification, is always performed under inert (e.g., N2) atmosphere. This work is the first report related to evaluating the possibility and efficiency of the grafting of acrylonitrile (AN) onto starch in presence of oxygen. Thus, corn starch (in both granular and gelatinized states) as well as soluble starch were grafted by AN using a ceric-carbohydrate redox initiating system. Graft copolymerizations were performed under nitrogen, air, and oxygen atmospheres at similar conditions. Grafting occurrence was verified using chemical and spectral proofs. The polymerization mechanism and kinetics were investigated by recording the... 

Acrylonitrile (AN) was grafted onto various natural and modified polysaccharides (i.e., gum arabic, gum tragacanth, xanthan gum, sodium alginate, chitosan, sodium carboxymethyl cellulose, hydroxyethyl cellulose, methyl cellulose) by using ceric-carbohydrate redox initiating system. After overcoming practical problems, mainly from the high viscosity of the aqueous solutions of the different substrates, the graft copolymerization reactions were run either in air or in N2 atmosphere under similar conditions. Grafting was confirmed using chemical and spectral (FTIR) proofs. The reactions were kinetically investigated using semi-empirical expressions and time-temperature profiles. An anomalous... 

A 1.5-V single supply, second order continuous-time bandpass filter, on a 0.6μm standard CMOS process is designed. The THD of the transconductor for a 0.7Vpp input, is -50dB at 10-MHz. In the proposed transconductor structure, the whole circuit, apart from a dc level-shifter based on a voltage doubler, is biased by a single 1.5-V supply. Due to this structure, a high current voltage doubler is not required and the whole filter draws less than 70μm current from this doubler making an on-chip voltage doubler feasible. Also, a new linear common-mode detector with high-frequency response is designed to stabilize the output common-mode voltage. © 2002 IEEE  

A very low voltage transconductor for video frequency range applications and compatible with standard CMOS technology is described. In the proposed transconductor, except the DC level shifter circuit (DCLS), the whole transconductor uses the main supply voltage [which can be as low as 1.5 V in a standard 0.6 μm CMOS technology] while the DCLS uses a simple charge-pump circuit as its supply voltage and has a very low current consumption. In addition, proper common-mode sense and charge-pump circuits are developed for this low-voltage application. Meanwhile, some techniques to improve the frequency response, linearity, and noise performance of the proposed transconductor are described. In a... 

Modified two-phase latch and flip-flop are introduced to implement a linear phase-detector (LPD) for 1/N-rate clock recovery applications. This technique greatly simplifies the required circuitry of the LPD and makes it suitable for higher speed applications while consuming less power compared to the conventional techniques  

A structured design of Subscriber Line Interface System and Circuit will be described. A high level synthesis allows extracting overall system and circuit requirements to satisfy the desired specifications, standards, and a robust implementation. For this purpose, first the output driving stage will be analyzed and then, dc, ac, and longitudinal balance feedbacks will be considered. Then based on extracted system specifications, optimum circuit design of line-driver will be described. High-level design of line-driver as the most important circuit block which is optimized for stability, accuracy, area, and power dissipation will be elaborated. © 2005 Springer Science + Business Media, Inc  

A combination of silica chloride and wet SiO2 was used as an effective deacetalizating agent for the conversion of acetals to their corresponding carbonyl derivatives under mild and heterogeneous condition  

A single 1.5 V supply, second order band-pass gm-C filter based on a low-voltage transconductor architecture in standard 0.6 um CMOS process is presented. A dc level shifter circuit (DCLS) is utilized at the input of the proposed transconductor to increase the dc level of the input signal. This makes the input transistors operate in the desired region and hence input voltage swing enhances. DCLS uses a simple voltage doubler as its supply while other parts of the circuit use the main 1.5 V supply. Proposed transconductor shows a THD of -60 dB for 1.4 Vpp,diff input signal with 1 MHz frequency. Also a proper common-mode detector circuit is developed for this low-voltage application. The... 

A structured design of Subscriber Line Interface System and Circuit will be described. A high level synthesis allows extracting overall system and circuit requirements to satisfy the desired specifications, standards, and a robust implementation. For this purpose, first the output driving stage will be analyzed and then, dc, ac, and longitudinal balance feedbacks will be considered. Then based on extracted system specifications, optimum circuit design of line-driver will be described. High-level design of line-driver as the most important circuit block optimized for stability, accuracy, area, and power dissipation will be elaborated  

This article explores the main tradeoffs in design of power and area efficient bandgap voltage reference (BGR) circuits. A structural design methodology for optimizing the silicon area and power dissipation of CMOS BGRs will be introduced. For this purpose, basic equations of the bandgap circuit have been adapted such that can simply be applied in the optimization process. To improve the reliability of the designed circuit, the effect of amplifier offset has been also included in the optimization process. It is also shown that the minimum achievable power consumption and area are highly depending on the fabrication process parameters especially sheet resistivity of the available resistors in... 

This paper studies the specifications of gated-oscillator-based clock and data recovery circuits (GO CDRs) designed for short haul optical data communication systems. Jitter tolerance (JTOL) and frequency tolerance (FTOL) are analyzed and modeled as two main design parameters for the proposed topology to explore the main tradeoffs in design of low-power GO CDRs. Based on this approach, a top-down design methodology is presented to implement a low-power CDR unit while the JTOL and FTOL requirements of the system are simultaneously satisfied. Using standard digital 0.18 μm CMOS technology, an 8-channel CDR system has been realized consuming 4.2 mW/Gb/s/channel and occupying a silicon area of...