Sharif Digital Repository

Carbon nanotubes are widely used in the design of nanosensors and actuators. Any defect in the manufactured nanotube plays an important role in the natural frequencies of these structures. In this paper, the effect of vacancy defects on the vibration of carbon nanotubes is investigated by using an atomistic modeling technique, called the molecular structural mechanics method. Vibration analysis is performed for armchair and zigzag nanotubes with cantilever boundary condition. The shift of the principal frequency of the nanotube with vacancy defect at different locations on the length is plotted. The results indicate that the frequency of the defective nanotube can be larger or smaller or... 

A compact, low power, clock frequency doubler circuit with no external devices designed and manufactured in a 0.5um CMOS technology. Proposed circuit generates a 4.096MHz output clock frequency from a 2.048MHz input clock while an automatic duty cycle control circuit reduces the sensitivity of the duty cycle of output clock to the duty cycle of input signal or process and temperature we variations. For this purpose, an accurate delayed clock is generated. structure besides MOSFET capacitors offers a impact and low power circuit. The area of the circuit is 0.08mm2 while consumes 380uArms SV power supply and drives 15pF capacitor load. Measured output duty cycle shows a variance of 2.7% from... 

A technique to reduce close-in phase noise in CMOS LC voltage controlled oscillators is proposed. In CMOS differential LC oscillators, the up-conversion of flicker noise mainly determines the close-in phase noise. The flicker noise of the bias current is a major component contributing to the overall low frequency noise. In this paper, a switched biasing technique to suppress the flicker noise of the bias circuit is presented. A 1.8v 2.4GHz differential LC VCO is designed in a 0.18u CMOS technology using this technique. With the proposed switching technique, the close in phase noise is improved as much as 15dB at 500 kHz offset. The simulated phase noise at the offsets of 500 kHz and 1 MHz is... 

A single 1.5 V supply, second order band-pass gm-C filter based on a low-voltage transconductor architecture in standard 0.6 um CMOS process is presented. A dc level shifter circuit (DCLS) is utilized at the input of the proposed transconductor to increase the dc level of the input signal. This makes the input transistors operate in the desired region and hence input voltage swing enhances. DCLS uses a simple voltage doubler as its supply while other parts of the circuit use the main 1.5 V supply. Proposed transconductor shows a THD of -60 dB for 1.4 Vpp,diff input signal with 1 MHz frequency. Also a proper common-mode detector circuit is developed for this low-voltage application. The... 

A structured design of Subscriber Line Interface System and Circuit will be described. A high level synthesis allows extracting overall system and circuit requirements to satisfy the desired specifications, standards, and a robust implementation. For this purpose, first the output driving stage will be analyzed and then, dc, ac, and longitudinal balance feedbacks will be considered. Then based on extracted system specifications, optimum circuit design of line-driver will be described. High-level design of line-driver as the most important circuit block optimized for stability, accuracy, area, and power dissipation will be elaborated  

In this paper, a fourth-order, 3.5-MHz, low-pass elliptic Gm-C filter employing low-noise, low-voltage transconductance amplifiers is presented. A new technique to enhance the linearity of the Gm-C filter is proposed. Furthermore, the nonlinear behavior of the filter caused by nonlinear behavior of transconductors with determined input amplitude is discussed. HSpice simulation results of the 1.8-V filter in a 0.18μm CMOS process show a THD of less than 44dB for 0.6Vpp input signal and an input-referred noise of less than 45 nV/√Hz in worst case. The current consumption of each OTA is 1.5-mA. © 2006 IEEE  

A size-dependent functionally graded Euler-Bernoulli beam model is developed based on the strain gradient theory, a non-classical theory capable of capturing the size-effect in micro-scaled structures. The governing equation and both classical and non-classical boundary conditions are obtained using variational approach. To develop the new model, the previously used simplifying assumption which considered the length scale parameter to be constant through the thickness is avoided in this work. As a consequence, equivalent length scale parameters are introduced for functionally graded microbeams as functions of the constituents' length scale parameters. Moreover, a generally valid closed-form... 

This article explores the main tradeoffs in design of power and area efficient bandgap voltage reference (BGR) circuits. A structural design methodology for optimizing the silicon area and power dissipation of CMOS BGRs will be introduced. For this purpose, basic equations of the bandgap circuit have been adapted such that can simply be applied in the optimization process. To improve the reliability of the designed circuit, the effect of amplifier offset has been also included in the optimization process. It is also shown that the minimum achievable power consumption and area are highly depending on the fabrication process parameters especially sheet resistivity of the available resistors in... 

In this paper, a new 1/4 rate clock linear phase detector (PD) structure for PLL-based clock and data recovery (CDR) circuits will be suggested. The proposed topology offers a more suitable PD for high speed applications compared to the conventional topologies. The effect of duty cycle variation on the operation of CDR has been also studied. Designed in a 0.18μm CMOS technology, the proposed PD consumes 16mA from a 1.8V voltage supply. © 2006 IEEE  

Micro-machining of face centered cubic (FCC) metallic materials is simulated via the theory of rate-dependent crystal plasticity. This approach accounts for slip systems and crystallographic orientations in its constitutive framework in order to accurately model the evolution of localized shear band formed during severe plastic deformation of crystalline materials. Through developing a user-defined subroutine in the ABAQUS/Explicit FE platform, the constitutive model is implemented and used to study the influence of workpiece crystallographic orientation on the cutting and thrust specific energies of the process. Due to the high rate of deformation, mechanical properties of texture can be... 

In this paper, the stability of delay differential equations (DDEs), describing self-excited vibrations in a micro-milling process, is investigated based on semi-discretization (SD) method. Due to the stubby geometry of micro-tools, the shear deformation and rotary inertia effects are considered for modeling the structure. The extended Hamilton's principle is used to derive a detailed dynamical model of the spinning micro-tool with the support of misalignment in which the gyroscopic effects cause coupling of equations. Considering the actual geometry of the micro-end mill, exact dynamic stiffness (DS) formulations are developed to investigate the tool's free vibration characteristics. The... 

In this paper, chatter instability of micro end mill tools is studied by taking into account the process damping effect. The actual geometry of the micro tool including shank, taper part and fluted section is considered in the analysis. Timoshenko beam theory is utilized to consider the shear deformation and rotary inertia effects due to short and thick beam-type structures of each parts of the micro tool. The extended Hamilton's Principle is used to formulate a detailed dynamical model of the rotating micro end mill. The governing equations are solved by assumed mode model expansion. An exact dynamic stiffness method is developed to investigate modal characteristics of the tool including... 

In this paper, a size-dependent formulation is presented for vibration analysis of micro-end mill tool. The formulation is developed based on the strain gradient elasticity theory in order to enhance the modeling capability of micro-size structures. Due to stubby geometry of micro-tool, the shear deformation and rotary inertia effects are considered in the derivation of equations. Hence, based on the strain gradient Timoshenko beam theory, the extended Hamilton's principle is used to formulate a detailed dynamical model of the rotating micro-tool. The dynamical model includes a set of partial differential equations with gyroscopic coupling produced due to the spindle rotation. The governing... 

This paper presents a top-down approach to the design of all-silicon CMOS-based fully integrated optical receivers. From the system-level requirements, we determine the optimum block-level specifications, based on which the individual building blocks are designed. Measurement results of the manufactured design show operation at data rates exceeding 2.5-Gbps/channel for the detector, the amplification and the clock and data recovery circuits. This proof of concept is the first step towards design optimized, completely integrated, multi-channel optical receivers for high-bandwidth short-distance chip-to-chip interconnects. © 2006 IEEE  

This paper investigates the dynamic pull-in behavior of microplates actuated by a suddenly applied electrostatic force. Electrostatic, elastic and fluid domains are involved in modeling. First-order shear deformation plate theory and classical plate theory are used to model the geometrically nonlinear microplates. The equations of motion are descritized by the finite element method. The effects of nonlinearity, fluid pressure, initial stress and different geometric parameters on dynamic behavior are examined. In addition, the influences of initial stress and actuation voltage on oscillatory behavior of microplates are evaluated. © 2009 Elsevier Masson SAS. All rights reserved  

A low-power delay-locked loop (DLL)-based clock and data recovery (CDR) circuit with a high-frequency tolerance is presented. The design of DLL clock generator is based on an analytical approach to satisfy the jitter requirements of the system. Meanwhile, a novel analogue phase interpolator (PI) has been employed for fine delay adjustment of the recovered clock. Using a charge-pump-based PI, it is possible to simplify the control circuit considerably and hence reduce the system power consumption. To improve the frequency-tracking ability of the system, a frequency control loop is also added to the proposed CDR system. Designed in conventional 0.18 μm CMOS technology and operating in 10 Gbps... 

The design of a Gm-C filter for High-Frequency applications is described in this paper. A low-pass, sixth-order elliptic Gm-C filter based on the new biquadratic architecture in 0.18 um CMOS process is designed with the proper dynamic rang. A simple structure of the high Q biquadratic filter is used to enhance the linearity and tunability of the filter. The cut off frequency of this filter is 33 MHz. It has a THD of -45 dB for 0.2 Vpp, 8 MHz signal. The complete filter including on-chip tuning circuit consumes only 0.8mA with 1.8 V single supply voltage. ©2006 IEEE  

A 1.5-V single supply, second order continuous-time bandpass filter, on a 0.6μm standard CMOS process is designed. The THD of the transconductor for a 0.7Vpp input, is -50dB at 10-MHz. In the proposed transconductor structure, the whole circuit, apart from a dc level-shifter based on a voltage doubler, is biased by a single 1.5-V supply. Due to this structure, a high current voltage doubler is not required and the whole filter draws less than 70μm current from this doubler making an on-chip voltage doubler feasible. Also, a new linear common-mode detector with high-frequency response is designed to stabilize the output common-mode voltage. © 2002 IEEE  

A very low voltage transconductor for video frequency range applications and compatible with standard CMOS technology is described. In the proposed transconductor, except the DC level shifter circuit (DCLS), the whole transconductor uses the main supply voltage [which can be as low as 1.5 V in a standard 0.6 μm CMOS technology] while the DCLS uses a simple charge-pump circuit as its supply voltage and has a very low current consumption. In addition, proper common-mode sense and charge-pump circuits are developed for this low-voltage application. Meanwhile, some techniques to improve the frequency response, linearity, and noise performance of the proposed transconductor are described. In a...