Sharif Digital Repository

2,4,6,8,10,12-Hexanitro-2,4,6,8,10,12-hexaazaisowurtzitane (2,4,6,8,10,12-hexanitro-2,4,6,8,10,12-hexaazatetracyclo dodecane (CL-20)-based polymer/plastic bonded explosives are used in propellant formulation. It can be predicted that CL-20-based nano-polymer/plastic bonded explosives are able to have reduced composite sensitivity and superior mechanical strength. In the current study, we have prepared two kinds of CL-20-based nano-polymer/plastic bonded explosives with ethylene-vinyl acetate copolymer and glycidyl azide polymer via the microemulsion method. Several visual techniques such as SEM/AFM/TEM techniques have been utilized for complete characterization of CL-20-based... 

All-solution-processed multilayer ZnO/Ag NWs/ZnO/PVP/PVA composite is introduced as a transparent conductive film (TCF) for optoelectronic applications. Unlike conventional film formation methods that impose high investment expenses, scalable spray coating is applied over the layers using a hand-made spray apparatus. The resulting TCF exhibits high transmittance (T, 86% at 550 nm) and low sheet resistance (Rs, 6 Ω/sq), which is comparable to the sputtered counterparts. The bending test demonstrates the flexibility of the multilayer TCF with no noticeable increase in Rs, even after 1500 bending iterations. Moreover, chemical stability test (exposure to a corrosive agent) and adhesion... 

This paper presents two effective methods to reduce power consumption of branch target buffer (BTB): 1) the first method is based on storing distance to next branch address in tag array instead of storing whole branch address, 2) the second method is to use a new field in data array of BTB namely Next Branch Distance (NBD) which holds distance of next branch address from current branch address. When a new hit is performed in BTB, based on NBD field, there would be no access through NBD number of instructions, so BTB can be shutdown not to consume power. The new architecture does not impose extra delay and reduction in prediction accuracy. Both methods were implemented and simulated using... 

This paper presents two effective methods to reduce power consumption of branch target buffer (BTB): 1) the first method is based on storing distance to next branch address in tag array instead of storing whole branch address, 2) the second method is to use a new field in data array of BTB namely Next Branch Distance (NBD) which holds distance of next branch address from current branch address. When a new hit is performed in BTB, based on NBD field, there would be no access through NBD number of instructions, so BTB can be shutdown not to consume power. The new architecture does not impose extra delay and reduction in prediction accuracy. Both methods were implemented and simulated using... 

In this paper, we present an experimental evaluation of transient effects on an embedded system which uses SRAM-based FPGAs. A total of 7500 transient faults were injected into the target FPGA using Power Supply Disturbances (PSD) and a simple 8-bit microprocessor was implemented on the FPGA as the testbench. The results show that nearly 64 percent of faults cause system failures and about 63 percent of the faults lead to corruption of the configuration data of the FPGA chip. © 2005 IEEE  

This paper presents an experimental evaluation of transient effects on SRAM-based FPGAs. A total of 9000 transient faults were injected into the target FPGA using Power Supply Disturbances (PSD). The results show that nearly 60 percent of faults cause system failures and about 58 percent of the faults lead to corruption of the configuration data of the FPGA chip. © 2005 IEEE  

In recent years, thin silver nanowires (Ag NWs) with diameters smaller than 150 nm have been synthesized by implementation of NaCl or FeCl3 as reaction promoters and high molecular weight polyvinylpyrrolidone (PVP) as the capping agent. However, the yield of Ag NWs still remains low, mostly due to the insufficient aspect ratio (AR) of the synthesized nanostructures and the production of Ag nanoparticles, which is an undesirable by product. This study proposes a modified technique to alleviate the problem by using a mixture of FeCl3/CuCl2 as the reaction promoter and two different types of PVP with molecular weight of 360 k and 40 k as the capping agents. The appropriate mixtures of... 

The brushless dc limited angle torque motor (LATM) has been widely used in areas of aerospace equipments, robot drives, optical scanning systems and any drive systems that require limited motion, ranging from the simple ON-OFF servo valves to the accurate tracking of a reference signal. This paper presents the optimum design procedure of a brushless direct current LATM to satisfy the functional requirements (FRs) and constraints using Independence axiom in axiomatic design (AD) approach. Also, to select the best manufacturing process plan, we consider both cost and thermal performance as two effective criteria, and evaluate available alternatives by computing information content in... 

This paper presents a comprehensive design procedure of a brushless DC limited angle torque motor (LATM) based on magnetic equivalent circuit analysis which predicts its performance and magnetic characteristics. Design of toroidally wounded armature and rotor with two pole tip segments are developed using selected ferromagnetic material and rare earth permanent magnets. Derivation of airgap and other motor dimensions and design parameters with their expressions are given. A finite element analysis verification of designed LATM using a 2D modeling and simulating package is presented. Performance characteristic of analytical model and FEA model of designed LATM is compared which validates the... 

SRAM-based FPGAs are currently utilized in applications such as industrial and space applications where high availability and reliability and low cost are important constraints. The technology of such devices is sensible to Single Event Upsets (SEUs) that may be originated mainly from heavy ion radiation. This paper presents a fault injection method that is based on emulated SEU on the configuration bitstrearn file of commercial SRAM-based FPGA devices to study the error propagation in these devices. To demonstrate the method, an Altera FPGA, i.e. the Flex10K200, and the ITC'99 benchmark circuits are used. A fault injection tool is developed to inject emulated SEU faults into the circuits.... 

The technology of SRAM-based devices is sensible to Single Event Upsets (SEUs) that may be induced mainly by high energy heavy ions and neutrons. This paper presents a framework for the evaluation of fault-tolerant designs implemented on SRAM-based FPGAs using emulated SEUs. The SEU injection process is performed by inserting emulated SEUs in the device using its configuration bitstream file. An Altera FPGA, i.e. the Flex10K200, and the ITC'99 benchmark circuits are used to experimentally evaluate the method. The results show that between 32 to 45 percent of SEUs injected to the device propagate to the output terminals of the device  

This paper presents a new cache scheme based on varying the size of sets in the set-associative cache hierarchically. In this scheme, all sets at a hierarchical level have same size but are fc times more than the size of sets in the next level of hierarchy where k is called division factor. Therefore the size of tag fields associated to each set is variable and it depends on the hierarchy level of the set it is in. This scheme is proposed to achieve higher hit ratios with respect to the two conventional schemes namely set-associative and direct mapping. The proposed scheme has been simulated with several standard trace files SPEC 2000 and statistics are gathered and analyzed for different... 

Dependability evaluation of embedded systems due to the integration of hardware and software parts is difficult to analyze. In this paper, we have proposed an experimental method to determine sensitivity to soft errors in an embedded system exploiting Altera SRAM-based FPGAs. The evaluation is performed using both the hardware and software parts of the embedded system in a single framework. To do this, the HDL hardware model of the target system as well as the C-written software codes of the target system, are required. Both permanent and transient faults are injected into the partially- or fully-synthesizable hardware of the target system and this can be performed during the design cycle of... 

Caches, which are comprised much of a CPU chip area and transistor counts, are reasonable targets for transient single and multiple faults induced from energetic particles. This paper presents: (1) a new fault detection scheme for tag arrays of cache memories and (2) an architectural cache to improve performance as well as dependability. In this architecture, cache space is divided into sets of different sizes and different tag lengths. Using the proposed fault detection scheme, i.e., GParity, when single and multiple errors are detected in a word, the word is rewritten by its correct data from memory and its GParity code is recomputed. The error detection scheme and the cache architecture... 

SRAM cache memories suffer from single event upset (SEU) faults induced by energetic particles such as neutron and alpha particles. To protect these caches, designers often use error detection and correction codes, which typically provide single-bit error detection and even correction. However, these codes have low error detection capability or incur significant performance penalties. In this paper, a protected cache scheme based on the variable associativity of sets is presented. In this scheme, cache space is divided into sets of different sizes with variable tag field lengths. The other remained bits of tags are used for protecting the tag using a new protection code. This leads to... 

In this paper, a new cache placement scheme is proposed to achieve higher hit ratios with respect to the two conventional schemes namely set-associative and direct mapping. Similar to set-associative, in this scheme, cache space is divided into sets of different sizes. Hence, the length of tag fields associated to each set is also variable and depends on the partition it is in. The proposed mapping function has been simulated with some standard trace files and statistics are gathered and analyzed for different cache configurations. The results reveal that the proposed scheme exhibits a higher hit ratio compared to the two well-known mapping schemes, namely set-associative and direct mapping,... 

The size and speed of SRAM caches of embedded systems are increasing in response to demands for higher performance. However, the SRAM caches are vulnerable to soft errors originated from energetic nuclear particles or electrical sources. This paper proposes a new protected cache scheme, which provides high performance as well as high fault detection coverage. In this scheme, the cache space is divided into sets of different sizes. Here, the length of tag fields associated to each set is unique and is different from the other sets. The other remained bits of tags are used for protecting the tag using a fault detection scheme e.g., generalized parity. This leads to protect the cache without... 

System fault-tree analysis is a technique for modeling dependability that is in widespread use. For systems such as embedded systems that include both hardware and software, the integration of hardware and software fault trees has proved problematic. In this paper, we present a method for reliability and safety analysis of embedded systems modeled by SystemC language. The evaluation is based on the fault trees generated from both hardware and software parts of the embedded systems described in the unified language. The unified modeling of both hardware and software of embedded systems using SystemC enables designers to be early aware from the safety and reliability of their designs more... 

Information integrity in cache memories is a fundamental requirement for dependable computing. As caches comprise much of a CPU chip area and transistor counts, they are reasonable targets for single and multiple transient faults. This paper presents: 1) a fault detection scheme for tag arrays of cache memories and 2) an architectural cache to improve dependability as well as performance. In this architecture, cache space is divided into sets of different sizes and different tag lengths. The error detection scheme and the cache architecture have been evaluated using a trace driven simulation with soft error injection and SPEC 2000 applications. The results show that error detection...