Loading...
Search for:
associativity
0.027 seconds
Proposing a Combined BTB and Data Cache Architecture for Modern Processors
, M.Sc. Thesis Sharif University of Technology ; Sarbazi Azad, Hamid (Supervisor)
Abstract
Modern pipelined processors use a memory array named Branch Target Buffer (BTB) to reduce the performance penalty due to conditional braches by predicting path of the branch and keeping useful history-based information for future accesses. Today BTB is a fixed size and small memory array located near the processor. By the way, BTB, in the best case, should be large enough to accommodate all conditional branches throughout the running program. Moreover, small size BTB presents much fast access and is practical on-chip storage for a system with limited power budget.
Considering role in the memory hierarchy, on the other hand, the system performance is highly correlated to the L1 data cache...
Considering role in the memory hierarchy, on the other hand, the system performance is highly correlated to the L1 data cache...