Sharif Digital Repository

Long Term Evolution (LTE) aims the peak data rates in excess of 300 Mb/s, which may appear to be challenging to achieve due to the existence of some blocks such as the turbo decoder. One efficient approach to achieve this throughput is by parallelizing the Log Maximum a Posteriori (MAP) algorithm in the turbo decoder. In fact, the interleaver is known to be a major challenging part of the turbo decoder due to its need to the parallel interleaved memory access. LTE uses Quadratic Permutation Polynomial (QPP) interleaver, which makes it suitable for the parallel decoding. In this thesis, first, we propose an efficient architecture for the QPP interleaver, called the Add-Compare-Select (ACS)... 

In this thesis, new boundary conduction mode boost PFCs are proposed and implemented for different power levels according to the characteristics and requirements of each power level. For medium power applications, we have proposed a new zero voltage switching PFC based on a synchronous boost converter which is controllable with conventional boundary conduction mode PFC control ICs without requiring any additional timing adjustment control circuits other than a special high side driver that consists of only low voltage components. Based on mathematical calculations, we have proposed two sipmle circuit solutions to reduce the high level of line current zero crossing distortion in the proposed...