Sharif Digital Repository

To capture on-chip memory locality, tolerate off-chip memory latency, and expeditiously process memory-bound GPGPU applications, Graphics Processing Units (GPUs) introduce a local L1D cache and a shared L2 cache within and between streaming multiprocessors (SMs), respectively. The L2 cache solves the problem of data coherency and sharing between SMs (unlike the L1D cache). Prior work shows that loading all data into the L2 cache without a proper mechanism to manage the input data rate, poses some challenges (e.g., cache contention/trashing, increased write-back traffic, and bandwidth inefficiency) and ultimately puts a lot of pressure on off-chip memory. In this paper, we make the... 

Using accelerators inside high speed servers can reduce execution time of applications and total power usage of the system. Sharing accelerator between virtual machines of a server decrease both cost and power, however it won’t provide the gained speedup of using dedicated accelerator for each virtual machines. Creation of an appropriate set of accelerators required for virtual machines, management of accesses to the accelerator, prioritizing and scheduling of requests and reconfiguration type of accelerator are the most important challenges that this project has been dealt with. The main objective of this project is implementing the necessary infrastructure to share an FPGA-based...