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Influential Factors in the Unstability of SRAM Cell and a Novel Structure for Improvement of Stability
, M.Sc. Thesis Sharif University of Technology ; Hajsadeghi, Khosro (Supervisor)
Abstract
Embedded SRAM unit is recognized as an important block in the systems on chip. In recent years due to an abrupt increase in the number of such systems which often work with battery, the priority of designing of low power circuits has been increased. Furthermore, increase in the number of transistors in the SRAM and increase in leakage current of MOS transistors with technology scaling have rendered the SRAM into the main energy consumer (from both static and dynamic view).In the writing operation due to the full swing of bit line, the dynamic power forms the main chunk of the consumptive power. The static consumptive power mostly happens due to the leakage current of broken cells in an array...
Design and Analysis of Low Voltage Low-power SRAM
, Ph.D. Dissertation Sharif University of Technology ; Hajsadeghi , Khosro (Supervisor) ; Sharifkhani, Mohammad (Supervisor)
Abstract
The explosive growth of battery operated devices has made low-power design a priority in recent years. Moreover, embedded SRAM units have become an important block in modern SoCs. The increasing number of transistor count in the SRAM units and the surging leakage current of the MOS transistors in the scaled technologies have made the SRAM unit a power hungry block from both dynamic and static perspectives. One of the key strategies for reducing power consumption is reducing the supply voltage to near or below the threshold voltage of the transistor. However, as supply voltage decreases to tackle the power consumption, the data stability of the SRAM cells have become a major concern in recent...
SRAM Cell Design for Low Power Applications
, M.Sc. Thesis Sharif University of Technology ; Haj Sadeghi, Khosrow (Supervisor)
Abstract
From the cache of the personal computers to the main memory unit of SOCs, medical and wearable chips, Static Random Access Memory (SRAM) is widely utilizes. Preferable performance for SRAM varies with regard to the operating field. For instance, high speed access and performance is emphasized in the design of the cache for PCs. In contrast, power consumption and the area of the memory are the key design considerations for SOCs. Hence, the field in which SRAM is used, should be thoroughly studied. SOCs and medical chips suffer limitations in design due to using batteries as the source of energy and SRAMs consume a significant part of total power and occupy a large area on these chips. One of...
Design of Low-Power Zero Temperature Coefficient (ZTC) CMOS Oscillators
, M.Sc. Thesis Sharif University of Technology ; Akbar, Fatemeh (Supervisor)
Abstract
The increasing demand for autonomous vehicles and reliable communication protocols and hardware interfaces, such as CAN bus and USB, underscores the necessity for stable clock sources that maintain a low temperature coefficient (TC) over wide temperature ranges. This demand is particularly emphasized in applications such as wearables, network sensors, downhole devices, WSNs, and IoT, where long-lasting battery life and frequency-stable clock sources over a broad temperature range (e.g. -20 °C to 100 °C) are crucial. Traditionally, variations in frequency caused by temperature have been mitigated by employing off-chip components like crystals or ceramic based oscillators, but this approach...