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- Type of Document: Ph.D. Dissertation
- Language: Farsi
- Document No: 40213 (05)
- University: Sharif University of Technology
- Department: Electrical Engineering
- Advisor(s): Atarodi, Mojtaba
- Abstract:
- Integration of radio transceivers results in developing low power low cost wireless systems and allows delivery of multimedia contents to battery-powered mobile terminals. Portable reception of digital video for hand-held devices is one of the applications, for which, some telecommunications standards have been developed in the recent years. This research deals with the integrated implementation of the radio frequency parts of the digital video receiver, especially the frequency synthesizer. The key aspects of the digital video reception system are the required signal to noise ratio, which is relatively high, wide band input signals and strong interferers in the receiving band.
In this thesis, the system design of the selected architecture for the digital video receiver has been done by hand calculations and structural simulations. The goal of this design is optimization of the system for integration, i.e. reduction of the area and power consumption, considering compatibility with the standard. According to the system analysis, the circuit of the wide band digital TV frequency synthesizer has been designed. The key features of the synthesizer circuit design are: optimizing of the wideband voltage controlled oscillator for compatibility of its phase noise performance with the standard, presenting a technique to reduce the required input swing of the current mode frequency dividers, using a programmable charge pump circuit for the phase locked loop stability over the wide frequency range and employing an adaptive frequency calibration block to control the oscillator frequency and the charge pump current. In addition, a divide-by-6 frequency divider for quadrature signal generation is proposed to reduce the required frequency range of the voltage controlled oscillator in the frequency synthesizer. Thus, all of the receiver bands can be covered with only one oscillator and the tuner area is reduced. In this thesis, behavior of passive mixers for direct conversion digital video receivers is analyzed and a bias circuit is proposed to minimize deviation of the mixer performance from typical case under process, temperature and supply voltage variations. A technique to suppress second and third order distortion in wideband low noise amplifiers has also been presented in this research. The proposed distortion cancellation technique leads to lower inter-modulation distortion products in the receive band and higher signal to noise plus interference ratio at the output of the receiver. According to the circuit and system analysis, two frequency synthesizer prototypes for digital video receivers have been fabricated in a 0.18um CMOS technology. Both of the circuits cover the target frequencies in the VHF, UHF and L bands. The measured phase noise, at 10 kHz and 1.45 MHz offset frequencies, are lower than -83 dBc/Hz and -131dBc/Hz, respectively. The measurement results show that the synthesizers meet the relatively stringent requirements of the digital video receivers and are able to be employed in low power small area systems.
- Keywords:
- Fractional Frequency Synthesis ; Phase Locked Loop (PLL) ; Voltage Controlled Oscillator ; Frequency Divider ; Low Noise Amplifier (LNA) ; Digital Video Receiver ; Integer Frequency Synthesizer
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