Loading...

An Adaptive Low-Power Sense Amplifier with Offset-Cancellation for High-Speed SRAM

Attarzadeh, Hourie | 2010

667 Viewed
  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 40877 (05)
  4. University: Sharif University of Technology
  5. Department: Electrical Engineering
  6. Advisor(s): Sharifkhani, Mohammad
  7. Abstract:
  8. A significant large amount of modern SOCs is occupied by SRAMs. Nowadays more than 70% of the Microprocessor area is occupied by SRAMs. This reinforces the need to design a more compact SRAM. With the increase in the processors speed, memories speed needs to be increased to enhance the overall throughput. Current Sense Amplifiers have partially solved the problem. However the area occupied by these amplifiers is still a large amount. The input offset is also not negligible. Due to their cascode configuration, these circuits cannot be scaled with the voltage scaling. In this thesis we proposed a new hybrid sense amplifier with an added phase, so the input offset can be cancelled with a large amount. Owing to its simplicity our scheme can work in the low voltages. The area occupied by the amplifier is two times smaller than its current counterparts. This scheme can work with the access time three times smaller than the conventional scheme with the same current cell and bitline capacitor. Access time reduction is dependent on the accuracy of offset cancellation. The increase in this amount leads to a larger power dissipation. In this thesis an adaptive method is used to optimize the power and speed. Two Integrated Circuit in the 0.18um CMOS technology is designed and implemented, one of which is tested. The other will be tested in the next months.
  9. Keywords:
  10. Sense Amplifier ; Static Random Access Memory (SRAM)Cell ; Offset Concellation ; Hybrid Amplifier

 Digital Object List

 Bookmark

No TOC