Loading...

Design of a Fault Tolerant ARM-Based Processor on FPGA

Esmaeeli, Siamak | 2011

781 Viewed
  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 42655 (05)
  4. University: Sharif University of Technology
  5. Department: Electrical Engineering
  6. Advisor(s): Rashidian, Bijan; Vosughi Vahdat, Bijan
  7. Abstract:
  8. The charged particles in space strike the silicon surface of an embedded system in a satellite and cause fault occurrence in its operation. So some methods should be employed to reduce the effects of the faults. The methods that are implemented in system level are widely used because of their low cost and high reliability. The processors are responsible for performing main processes in embedded systems. On the other hand, the ARM processors are good choices for utilizing in satellites because of their low size, low power consumption and high performance. Also, FPGAs have made a major improvement in embedded system design. So with implementing a fault tolerant ARM processor on an FPGA, we can design a suitable embedded system for space applications. In this thesis the ARM9TDMI processor is selected for design because of its appropriate architecture for implementing on FPGA. The soft errors in implemented processor are tolerated with using various methods. The errors in register file are detected and corrected with employing narrow-width values and extended Hamming code. Narrow-width value can be represented with half number of bits of full data width. A new decoder has been proposed for decoding extended Hamming code that is implemented in interleave manner. The obtained results of fault injection simulation show the error probability of a register file that is protected with the proposed method is less than the error probability of similar register file that is protected with other methods. Also, the area overhead of the proposed method is less than the area overhead of Triple Modular Redundancy (TMR) technique. Other parts of the processor are protected with full time redundancy scheme. The designed processor is implemented on a Xilinx FPGA from Virtex-4 family (XC4VSX55) and is evaluated with fault injection simulation. The obtained results show that if the register file of the processor is scrubbed each 5 minutes, the probability of failure in operation of the processor is approximately zero
  9. Keywords:
  10. Register File ; Advanced RISC Machine (ARM) ; Fault Tolerance ; Extended Hamming Code ; Narrow Width Values

 Digital Object List

 Bookmark

No TOC