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Design Tradeoffs of SSD Implementations on Reconfigurable Devices and ASICs

Faridmoayer, Reza | 2012

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  1. Type of Document: M.Sc. Thesis
  2. Language: English
  3. Document No: 42949 (55)
  4. University: Sharif University of Technology, International Campus, Kish Island
  5. Department: Science and Engineering
  6. Advisor(s): Asadi, Hossein
  7. Abstract:
  8. Solid-State Drives (SSDs) are replaced to a great portion of Hard Disk Drives (HDDs) in personal computers, servers, and supercomputers due to their high reliability, shock resistance, low power consumption, and high performance. SSDs utilize either NAND or NOR flash chips in the drive backend logic to persistently store user data. Since NAND/NOR flash chips incur from limited number of write endurance and high write/erase operation latency, they use a controller called Flash Translation Layer (FTL) to alleviate these limitations. As the performance of commercially off-the-shelf (COTS) SSDs is tuned for few mainstream applications, COTS SSDs provide limited throughput for variety of applications used in enterprise storage systems, server-centric storage architectures, and high performance computing. But, unlike COTS SSDs, reconfigurable SSDs can be adapted for an application running on a server or for an application requesting I/Os to/from a storage system. To design a reconfigurable SSD, the FTL should be implemented in reconfigurable architectures. In this thesis, we have proposed a novel FTL which allows triggering the page-level Garbage Collection mechanism once the number of blocks in a flash element with predefined valid pages is less than a certain threshold. Simulation results show that as compared with the baseline model, our proposed method significantly improves the performance while imposes a negligible write endurance overhead to the flash chips. The proposed method has been profiled and implemented on Xilinx ML403 evaluation board. In our experimental setup, we use simulation tools such as DiskSim to verify the efficiency of our proposed method. In our experiments, Intel® VTune™ Performance Analyzer is utilized to profile and partition the proposed FTL
  9. Keywords:
  10. Flash Memory ; Reconfigurable Architecture ; Solid State Disk Drive ; High-performance Solid State Disk Drive (SSD) ; Flash Translation Layer (FTL)

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