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A Novel Bitline Leakage-Free Current Sense Amplifier with Offset Cancelation for Sub-Threshold SRAM

Zamani, Milad | 2012

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 43174 (05)
  4. University: Sharif University of Technology
  5. Department: Electrical Engineering
  6. Advisor(s): Sharifkhani, Mohammad
  7. Abstract:
  8. A significant large amount of modern SOCs is occupied by SRAMs. Nowadays more than 70% of the Microprocessor area is occupied by SRAMs. The fast growth of battery-operated portable applications has compelled the SRAM designers to consider subthreshold operation as a viable choice to reduce the power consumption. In most such applications, the speed of the SRAM is not the challenging parameter therefore the thrust toward low power design influence the design choices in various parts of the SRAM architecture. With technology scaling to the nanometer, Bitline leakage current and offset voltage deteriorate SRAM reading performance since SRAM cell current is close to the Bitline leakage current. Based on the DRSRAM timing, this paper presents a novel sense amplifier design which cancels the input offset current and Bitline leakage current with a novel switching scheme. The mitigation of the Bitline leakage allows for 10 times improvement in the read transaction speed compared to the conventional SA under the same timing with 100nA Bitline leakage current. The new sense amplifier shows %63 energy delay product improvement in comparison with the conventional SA for 0.3V subthreshold SRAM in 90nm TSMC CMOS model
  9. Keywords:
  10. Static Random Access Memory (SRAM)Cell ; Sense Amplifier ; Offset Concellation ; Bitline Leakage Current ; Sub-Threshold Voltage

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