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A Survey and Practical Comparison of Top Techniques on Fault tolerant CPU Design

Zamani Foroushani, Javad | 2012

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 43720 (05)
  4. University: Sharif University of Technology
  5. Department: Electrical Engineering
  6. Advisor(s): Tabandeh, Mahmoud
  7. Abstract:
  8. Confronting with cosmic rays in electronic parts of space systems, especially in processors and their peripherals, has always been noteworthy topic. By decreasing the aspects of transistors and their voltages, fault occurrence problem in digital integrated circuits not only has been increased in space systems, but also infects on mission critical systems that work at ground level. Since there are many reports about the effect of high energy particles, like neutrons which are present in earth atmosphere, in sub-100 nm digital circuits.In this thesis we are discussing about architecture level techniques for hardening processors against soft errors of radiation.It has been done for each part of processor independently.Based on features of that part and requirements of nowadays systems, we select the best practical method for any part. In each part that old methods weren't efficient, we try to propose a new method which is match for modern CMOS technologies. Specifically for protecting of different types of memories and register files we select particular Reed-Solomon codes for the first time, that have very optimum encoder and decoder circuit in area and delay, but have high efficiency in error correction so that are suitable for modern memories. However suggested codes are comparable circuit delay and area with best traditional codes, but they have much higher error correction ability.In all stages, it is considered that selected designs to be appropriate for implementation in ASIC level with ordinary and available standard cells and for implementation with FPGA. Also we try to select solutions independent of processor architecture in order to be efficient for different types of processor. In addition, in order for our results to be useful for wide range of applications, our target are various levels of hardening. Also we have implemented our proposed methods in any section, and compare implementation results to select the best practical methods be appropriate for modern technologies. At the end, we have proposed final and complete processor design in three levels of fault tolerance ability.

  9. Keywords:
  10. Soft Error ; Reed-Solomon Code ; TMR Method ; Fault Tolerance ; Extended Hamming Code ; Processors ; Multi Bit Upset

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