A 12-bit, 40MS/s, Low Power Pipelined SAR ADC

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Khojasteh Lazarjan, Vahid | 2013

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Type of Document: M.Sc. Thesis
Language: Farsi
Document No: 44052 (05)
University: Sharif University of Technology
Department: Electrical Engineering
Advisor(s): Haj Sadeghi, Khosro
Abstract:
High resolution and low power analog to digital converters are used in wireless communication receivers, Sensor Networks and Medical Instrumentations. Reducing power consumption at a high conversion rate is one of the most basic challenges for these converters. Pipelined SAR structure is considered for 40-50 MS/s and 10-12 bits, and is of interest because of consuming low power and using a small area. Besides using Pipelined SAR structure, circuit level and system level modifications are also proposed to decrease the power consumption. The ADC is designed in 0.18µm CMOS technology with 1.2v supply voltage. The results show 4.5mW power consumption, when ENOB is 11.04bit, which is very low power consumption for 40MS/s in this technology
Keywords:
Analog to Digital Converter ; Pipeline Converter ; Successive Approximation Register (SAR)

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