Deign of 10 Bit 200 MS/s Pipeline Analog to Digital Converter in 0.18 um

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Ghaed Rahmati, Hanie | 2013

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Type of Document: M.Sc. Thesis
Language: Farsi
Document No: 44495 (05)
University: Sharif University of Technology
Department: Electrical Engineering
Advisor(s): Haj Sadeghi, Khosro
Abstract:
High speed data converter are very often used in telecommunication systems. Since these systems are increasingly used in mobile foem reducing the power consumption in these circuits is of great importance. The goal of this project was to design a pipeline 10 bit converter for a sample rate 200MS/s with a power consumption of 35 mW for the input level of 1Vp-p and a 1.8V power supply in 0.18um CMOS technology.
To reach these goals, a number of low power techniqes are proposed in various levels of abstraction. In system level, the sampling and feedback capacitors is optimized analytically which leads to simple back-envelope formulas to calculate the optimum values. In circuit level, a opamp-sharing by using a new opamp structure is proposed which significantly reduces the power consumption. To reduce the nonlinearity due to opamp-sharing, a new structure of MDAC is proposed. The pipeline ADC is implemented in Cadence software environment. The final design is a 10 bit analog to digital converter with a power consumption of 35mW, SNDR=59.4 dB and SFDR=68.7 dB for the input rate of Fin=5.023MHz, ENOB=9.58 and DNL<0.5 LSB and INL<0.5LSB
Keywords:
Analog to Digital Converter ; Pipeline Converter ; Low Power System ; High Speed Data Converter ; Opamp Sharing

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