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Accelerated FPGA-Based NOC Simulation With Software Configuration

Mardani Kamali, Hadi | 2013

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 44905 (19)
  4. University: Sharif University of Technology
  5. Department: Computer Engineering
  6. Advisor(s): Hesabi, Shahin
  7. Abstract:
  8. ITRS shows next generation of Multiprocessor System on Chip (MPSoCs) designs will contain hundreds of heterogeneous cores, running at different speeds and voltage levels. Networks-On-Chip (NoC) provide a structured way of realizing interconnections on silicon, and obviate the limitations of bus-based solution. As the number of components in MPSoCs increases, the interconnect schemes based on NoC approach are increasingly used. However, NoC designs have many power, area, and performance trade-offs in topology, buffer sizes, routing algorithms and flow control mechanisms, hence the study of new NoC designs can be very time-intensive.
    To address these challenges, we propose a new FPGA-based NoC Simulator with software configuration ability. This fast and flexible simulator has four main advantages. (I) we designed a gate-level structural based design which achieve to 90× speedup against software simulators; (II) our proposed architecture is the first hardware-based simulator which support Adaptive Routing based on Centralized structure; (III) we implemented a virtualized partitioning method which can instantiate large NoCs and the size of FPGA is not a limitation for large NoCs; and (IV) we model programmable switches which can replace with routers. When the concern of NoC designers is power consumption of the NoC, they can use switches for reducing power. We demonstrate that an implementation of our simulator on a Virtex-6 FPGA can achieve over 90× speedup over the cycle-based software simulator Booksim, while maintaining the same level of simulation accuracy
  9. Keywords:
  10. Network-on-Chip (NOC) ; Simulation ; Field Programmable Gate Array (FPGA)

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