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Design of Power Distribution Network in 3D ICs Thesis Submitted

Zabihi, Masoud | 2013

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 45291 (05)
  4. University: Sharif University of Technology
  5. Department: Electrical Engineering
  6. Advisor(s): Sarvari, Reza
  7. Abstract:
  8. Delay of Interconnects in modern digital ICs is several times greater than delay of gates. One proper measure for this problem is to shorten interconnects length by using three dimensional structures instead of conventional two dimensional structures. In these structures TSVs (Through Silicon Vias) make connection between stratums. Power integrity in 3D ICs necessitates power distribution networks to have minimum IR drop and Ldi/dt noise. In this dissertation we design power distribution network considering IR drop and Ldi/dt noise margin. We expand a mathematical model which represents differential equation of power distribution in the surface of each stratum. Using this expanded model we can analyzes not only non-uniform current density but also non-uniform decoupling capacitor density at the surface of stratums. Moreover, a closed form formula for impedance of TSVs from point of view of top stratum is derived. In this research we analyze effects of allocating different amount of decoupling capacitor on noise and we propose an optimal percentage of memory surfaces which should be allocated to decoupling capacitors. Our research reveals that allocating higher values to decaps does not necessarily result in noise reduction. For example, for periodic switching cycle, allocating 9% of DRAM Dies area to decaps results in higher noise levels in comparison with other percentages. To optimize the design, considering all impedance resonances is vital. Designers should be aware that these resonance must not match with clock frequency and it’s harmonics. Moreover effect of Decreasing in DRAM thickness on noise is investigated in this thesis. Results show that Decreasing DRAM thickness may result in IR drop reduction, but does not affect voltage fluctuations so much. It is owing to large package inductance. A possible solution for reducing voltage fluctuation would be adding capacitor and decreasing package inductance. In the other part of this thesis we investigate optimal geometry for a hot spot. If shape of the hot spot be rectangular, we can find an optimal value for proportion of length to width of hot spot. This value specify proportion of sheet resistances in x and y directions. The results show that when proportion of sheet resistance in x direction to sheet resistance to y direction is equal with proportion of width to length, noise will be minimum value at the center of hot region. Furthermore, we derived a closed-form formula for worst-case-scenario noise in a 3D IC with three stratums. This formula would easily be expanded to a 3D IC with any number of stratums
  9. Keywords:
  10. Noise ; Ohmic (Joule)Dissipation ; Three Dimentional ICs ; Through Silicon Vias (TSV)

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