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A Dependable Routing Architecture for Reconfigurable Devices

Yazdanshenas, Sadegh | 2014

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 45593 (19)
  4. University: Sharif University of Technology
  5. Department: Computer Engineering
  6. Advisor(s): Asadi, Hossein
  7. Abstract:
  8. Reconfigurable devices are a popular platform for fast prototyping of digital system due to having high performance of hardware implementation along with flexibility of software. However, reconfigurable devices suffer from area, performance and dependability gaps in comparison with their Application Specific Integrated Circuit (ASIC) counterparts, which greatly limits their application.
    The dependability gap originates from the sensitivty of configuration memory to soft errors. When a reconfigurable device configuration memory is affected by soft errors, their configuration will be invalid until reconfigured. Since the routing fabric is the origion of over 80% of soft errors in configuration memory,the focus of the proposed methods is on the routing fabric. In this thesis,three architectures are proposed for the routing fabric. In the first architecture,switch box behaviour to soft errors is throughly analyzed. Using this analysis,a redundant routing scheme using asymetric SRAM cells is proposed. This architecture allows achieving any desired level of dependability at the cost of a porportinate area overhead. In the second architecture, a circuitry capable of turning off SRAM cells is proposed to allow different parts of the device to be turned off. By turning off configuration cells, they are no longer susceptible to soft errors. Experimental results demonstrate that the number of configuration cells in connection blocks and switch boxes are reduced by 77% and 5% respectively.
  9. Keywords:
  10. Dependability ; Routing ; Soft Error ; Field Programmable Gate Array (FPGA) ; Static Random Access Memory (SRAM)Cell

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