Compensation and Calibration of ADCs

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Khanmohammad, Hesam | 2014

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Type of Document: M.Sc. Thesis
Language: Farsi
Document No: 45901 (05)
University: Sharif University of Technology
Department: Electrical Engineering
Advisor(s): Sharif Khani, Mohammad
Abstract:
Increasing demand for high-speed and high-resolution ADCs as much as low-power ones and on the other hand, the obstacles in the way of reaching them make calibration and compensation methods more significant for obtaining ADCs with the better specs. Among the cases which need modification, the modification of C-2C-based SAR ADCs, which can decrease the power significantly, and the modification of time-skew error of time-interleaved ADCs, which is the main and the most challenging error in this type of ADCs, could be the two of the effective ways to making the State-of-the-Art ADCs. In this project for the first time, a novel compensation method for C-2C parasitic charges is proposed which makes a 10bit C-2C-based SAR ADC have 9.3 effective number of bits (ENOB) and INL less than 1LSB. Moreover, a new time-skew error calibration method is proposed by which a 4channel 4GS/s 7bit resolution time-interleaved ADC experiences 25dB and 21dB enhancement in SNDR and SFDR respectively. Both methods are designed and applied to appropriate ADCs in 0.18µm process
Keywords:
Compensation ; Calibration ; Time Interleaved Converter ; Successive Approximation Register (SAR) ; Analog to Digital Converter

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