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An efficient STT-Ram last level cache architecture for GPUs

Samavatian, M. H ; Sharif University of Technology

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  1. Type of Document: Article
  2. DOI: 10.1109/DAC.2014.6881524
  3. Abstract:
  4. In this paper, having investigated the behavior of GPGPU applications, we present an effcient L2 cache architecture for GPUs based on STT-RAM technology. With the increase of processing cores count, larger on-chip memories are required. Due to its high density and low power characteristics, STT-RAM technology can be utilized in GPUs where numerous cores leave a limited area for on-chip memory banks. They have however two important issues, high energy and latency of write operations, that have to be addressed. Low data retention time STT-RAMs can reduce the energy and delay of write operations. However, employing STT-RAMs with low retention time in GPUs requires a thorough investigation on the behavior of GPGPU applications based on which the STT-RAM based L2 cache is architectured. The STT-RAM L2 cache architecture proposed in this paper, can improve IPC by more than 100% (16% on average) while reducing the average consumed power by 20% compared to a conventional L2 cache architecture with equal on-chip area
  5. Keywords:
  6. GPGPU Application ; GPU ; Retention Time ; STT-RAM ; Cache memory ; Computer aided design ; Program processors ; Data retention time ; Last-level caches ; Low-power characteristics ; Processing core ; Write operations ; Random access storage
  7. Source: Proceedings - Design Automation Conference ; 2-5 June , 2014 , pp. 1-6 ; ISSN: 0738100X ; ISBN: 9781479930173
  8. URL: http://ieeexplore.ieee.org/document/6881524/?tp=&arnumber=6881524&url=http:%2F%2Fieeexplore.ieee.org%2Fxpls%2Fabs_all.jsp%3Farnumber%3D6881524