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Time-scalable mapping for circuit-switched GALS chip multiprocessor platforms

Foroozannejad, M. H ; Sharif University of Technology

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  1. Type of Document: Article
  2. DOI: 10.1109/TCAD.2014.2299958
  3. Abstract:
  4. We study the problem of mapping concurrent tasks of an application to cores of a chip multiprocessor that utilize circuit-switched interconnect and global asynchronous local synchronous (GALS) clocking domains. We develop a configurable algorithm that naturally handles a number of practical requirements, such as architectural features of the target platform, core failures, and hardware accelerators, and in addition, is scalable to a large number of tasks and cores. Experiments with several real life applications show that our algorithm outperforms manual mapping, integer linear programming-based mapping after ten days of solver run time, and a recent packet-switched network on chip-based task mapper through which, we underscore the unique requirements of task mapping for circuit-switched GALS architectures
  5. Keywords:
  6. Algorithms ; Asynchronous sequential logic ; Integer programming ; Microprocessor chips ; Multiprocessing systems ; Architectural features ; Chip Multiprocessor ; Concurrent tasks ; GALS architecture ; Hardware accelerators ; Packet-switched ; Practical requirements ; Real-life applications ; Mapping
  7. Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ; Vol. 33, issue. 5 , May , 2014 , p. 752-762
  8. URL: http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=6800097&url=http%3A%2F%2Fieeexplore.ieee.org%2Fiel7%2F43%2F6800047%2F06800097.pdf%3Farnumber%3D6800097