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- Type of Document: Article
- DOI: 10.1145/2593069.2593166
- Abstract:
- With current memory scalability challenges, Phase Change Memory (PCM) is viewed as an attractive replacement to DRAM. The preliminary concern for PCM applicability is its limited write endurance that is highly affected by pro-cess variation in nanometer regime. This increases the vari- ation in cell lifetime resulting in early and sudden reduc- tion in main memory capacity due to wear-out of few cells. When some memory pages reach their endurance limits, other pages may be far from their limits even when using a perfect wear-leveling. Recent studies have proposed redi- rection or correction schemes to alleviate this problem, but all suffer from poor throughput or latency. On contrary, we present On-Demand Page Paired PCM (OD3P), a technique that mitigates the problem of fast failure of pages by redi- recting them onto other healthy pages, leading to gradual capacity degradation. Compared to a state-of-the-art error correction scheme for PCM, our experiments indicated that OD3P can improve PCM time-to-failure and system perfor- mance (IPC) by 12% and 14%, respectively, under multi- threaded and multi-programmed workloads
- Keywords:
- Computer aided design ; Error correction ; Capacity degradation ; Correction schemes ; Error-correction schemes ; Lifetime ; Nano-meter regimes ; Page Pairing ; Phase change memory (pcm) ; Write endurances ; Dynamic random access storage
- Source: Proceedings - Design Automation Conference ; 2014
- URL: http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=6881391&url=http%3A%2F%2Fieeexplore.ieee.org%2Fxpls%2Fabs_all.jsp%3Farnumber%3D6881391